evaluation using NanoBridge
® FPGA. Power consumption and miniaturization
effect were observed using a NanoBridge
® FPGA. Significant reduction of power
consumption and size was observed through the evaluation of the experiment.
The tape model used in conventional finite automaton were shown to be replaced
with Embedded Automaton (EA) through the experimental implementation of GPE
architecture using a NanoBridge
® FPGA. The implementation process of GPE
architecture was verified using NanoBridge
® FPGA. The possibility of soft error
occurrence is also reduced in space applications by eliminating large memory cells.
Some limitation exists for modifying application programs, and dynamic program
loading is not easy at present. However, the premises of embedded system are
different from those of conventional enterprise system in that unlimited modification
is not required, and no fundamental difficulties have been found. Since program
memories are reduced significantly, the remarkable advantage of low power consumption, which is found in conventional dynamically reconfigurable processors
[5], is expected as well.
As for the system performance of atomic switch processor elements based on the
GPE architecture, two kinds of simplification are realized, and real-time performance
is improved. Firstly, time is handled as basic data by the system. Therefore, the
virtualization of time using software interrupt is no longer necessary. Secondly,
concurrency inhered in system design is realized as physically concurrent process,
and hence virtualization using serialization of processes or tasks by multi-process
operating systems or multi-task operating systems is no longer required. Barrier
synchronization of concurrent processes can be performed on fine-grained or coarsegrained implementation. In consequence, simplified synchronization of multiple
processes and/or tasks of concurrent real-time systems can be realized.
In the technological road map point of view, system level programmable devices
is forecasted to be standardized after the era of System-on-a-chip (SoC) and System
in package (SiP) by the extended Makimoto’s Wave [33] shown in Fig. 20. That is
called as “Highly flexible super integration (HFSI)” in [33]. The right-most surge in
the Makimoto’s waves shown in [33] is considered as one of the design target of
atomic switch FPGAs based on GPE architecture, because the technology trend
shown by the Makimoto’s waves still holds.
Standard
discretes
Custom
LSIs
MicroProcessors
and memory
ASICs
Field
Programmability
‘57
‘67
‘77
‘87
‘97
‘07
‘17
Standardization
Customization
SoC/SiP
HFSI
Highly flexible
super integration
Fig. 20 Extended Makimoto’s Wave [33]
56
H. Hihara et al.
® FPGA. Power consumption and miniaturization
effect were observed using a NanoBridge
® FPGA. Significant reduction of power
consumption and size was observed through the evaluation of the experiment.
The tape model used in conventional finite automaton were shown to be replaced
with Embedded Automaton (EA) through the experimental implementation of GPE
architecture using a NanoBridge
® FPGA. The implementation process of GPE
architecture was verified using NanoBridge
® FPGA. The possibility of soft error
occurrence is also reduced in space applications by eliminating large memory cells.
Some limitation exists for modifying application programs, and dynamic program
loading is not easy at present. However, the premises of embedded system are
different from those of conventional enterprise system in that unlimited modification
is not required, and no fundamental difficulties have been found. Since program
memories are reduced significantly, the remarkable advantage of low power consumption, which is found in conventional dynamically reconfigurable processors
[5], is expected as well.
As for the system performance of atomic switch processor elements based on the
GPE architecture, two kinds of simplification are realized, and real-time performance
is improved. Firstly, time is handled as basic data by the system. Therefore, the
virtualization of time using software interrupt is no longer necessary. Secondly,
concurrency inhered in system design is realized as physically concurrent process,
and hence virtualization using serialization of processes or tasks by multi-process
operating systems or multi-task operating systems is no longer required. Barrier
synchronization of concurrent processes can be performed on fine-grained or coarsegrained implementation. In consequence, simplified synchronization of multiple
processes and/or tasks of concurrent real-time systems can be realized.
In the technological road map point of view, system level programmable devices
is forecasted to be standardized after the era of System-on-a-chip (SoC) and System
in package (SiP) by the extended Makimoto’s Wave [33] shown in Fig. 20. That is
called as “Highly flexible super integration (HFSI)” in [33]. The right-most surge in
the Makimoto’s waves shown in [33] is considered as one of the design target of
atomic switch FPGAs based on GPE architecture, because the technology trend
shown by the Makimoto’s waves still holds.
Standard
discretes
Custom
LSIs
MicroProcessors
and memory
ASICs
Field
Programmability
‘57
‘67
‘77
‘87
‘97
‘07
‘17
Standardization
Customization
SoC/SiP
HFSI
Highly flexible
super integration
Fig. 20 Extended Makimoto’s Wave [33]
56
H. Hihara et al.