been check by Takeuchi of JAXA. For this evaluation, 128 k-bit atomic-switch
ROM was used. We have not observed SEE, showing that SEE cross section is at
least 100 times lower than that of NAND flash. And this result is much lower than
that of SRAM.
6 FPGA Accelerator
Combination of CPU and nonvolatile FPGA accelerator (that is SoC FPGA) provides both the programmability and the high energy efficiency, especially for
Internet-of-Things (IoT) applications or wireless sensor nodes [21]. Figure 11
shows the block diagram of CPU and atomic-switch based FPGA for accelerator
[22]. Since the data transfer in the chip is one of the performance bottlenecks, three
kinds of data paths (DPs) are implemented: DP(1) through the register connected to
data bus for peripheral modules, DP(2) to directly read/write SRAM by FPGA, and
DP(3) for connecting modules outside of chip. Isolation cells are placed on the edge
of FPGA core. System operation with CPU and FPGA is done by vectored interrupt
scheme and specific 64 Byte mail-box register. Atomic switch constitutes both codeROM [23] and nonvolatile FPGA by the same process. The chip is fabricated by a
65 nm CMOS process (shown in Fig. 7). Since the voltage stress during the
operation is different for each other, one transistor and one resistor (1T1R) cell
structure is used for ROM and 1T2R (or CAS) for FPGA.
A 32-bit cyclic redundancy check (CRC32) is used to evaluate the energy
efficiency of MCU with no help of FPGA. The software process in the CPU operates
up to 25 MHz when the operation voltage (V DD ) is 0.41 V. At this condition the
highest power efficiency for CPU of 33 μW/MHz is achieved. The CRC32 execution
is off-loaded from CPU to the configured FPGA by waking up when necessary. Data
2.5
3
3.5
4
4.5
10
-8
10
-9
10
-10
10
-11
2.5
3
3.5
4
4.5
1.4
1.5
1.6
1.7
1.8
1.9
1000/T (K -1 )
1000/T (K -1 )
Atomic switch
nMOSFET
Atomic switch
nMOSFET
150⁰C
25⁰C
-40⁰C
85⁰C
25⁰C
Current (A)
Resistance (kΩ)
(a)
(b)
Fig. 10 (a) Temperature dependence of on resistance and (b) that of off current for atomic switch
and nMOSFET
28
T. Sakamoto et al.
ROM was used. We have not observed SEE, showing that SEE cross section is at
least 100 times lower than that of NAND flash. And this result is much lower than
that of SRAM.
6 FPGA Accelerator
Combination of CPU and nonvolatile FPGA accelerator (that is SoC FPGA) provides both the programmability and the high energy efficiency, especially for
Internet-of-Things (IoT) applications or wireless sensor nodes [21]. Figure 11
shows the block diagram of CPU and atomic-switch based FPGA for accelerator
[22]. Since the data transfer in the chip is one of the performance bottlenecks, three
kinds of data paths (DPs) are implemented: DP(1) through the register connected to
data bus for peripheral modules, DP(2) to directly read/write SRAM by FPGA, and
DP(3) for connecting modules outside of chip. Isolation cells are placed on the edge
of FPGA core. System operation with CPU and FPGA is done by vectored interrupt
scheme and specific 64 Byte mail-box register. Atomic switch constitutes both codeROM [23] and nonvolatile FPGA by the same process. The chip is fabricated by a
65 nm CMOS process (shown in Fig. 7). Since the voltage stress during the
operation is different for each other, one transistor and one resistor (1T1R) cell
structure is used for ROM and 1T2R (or CAS) for FPGA.
A 32-bit cyclic redundancy check (CRC32) is used to evaluate the energy
efficiency of MCU with no help of FPGA. The software process in the CPU operates
up to 25 MHz when the operation voltage (V DD ) is 0.41 V. At this condition the
highest power efficiency for CPU of 33 μW/MHz is achieved. The CRC32 execution
is off-loaded from CPU to the configured FPGA by waking up when necessary. Data
2.5
3
3.5
4
4.5
10
-8
10
-9
10
-10
10
-11
2.5
3
3.5
4
4.5
1.4
1.5
1.6
1.7
1.8
1.9
1000/T (K -1 )
1000/T (K -1 )
Atomic switch
nMOSFET
Atomic switch
nMOSFET
150⁰C
25⁰C
-40⁰C
85⁰C
25⁰C
Current (A)
Resistance (kΩ)
(a)
(b)
Fig. 10 (a) Temperature dependence of on resistance and (b) that of off current for atomic switch
and nMOSFET
28
T. Sakamoto et al.