6.3 ReConfigurable CAM Extension to CMOS
89
Table 6.4
CMOS CAM/SRAM comparison with state-of-the-art [©2017 IEEE]
This work
[6]
[81]
[82]
[83]
Technology
28 nm FDSOI
28 nm FDSOI
32 nm
65 nm
0.13
µm
Transistors/cell
6T
6T
11T
10T
9T + Read
Area/cell (µm 2
)
0.197
µm 2 a
0.152
µm 2
–
3.3
20
Array size
128
× 64
64
× 64
(64
× 64)
× 4
128
× 128
128
× 32
Frequency (VDD)
1.56 GHz (0.9 V) b
8.90 MHz (0.38 V) c
370 MHz (1 V)
500 MHz (1 V)
250 MHz (1 V)
Energy/search/bit
(fJ)
0.13 (0.9 V)
0.6 (1 V) 0.41 (0.75V)
1.07 (1 V) 0.3 (0.5 V)
0.77 (1.2V)
1.87 (1 V)
Match-line
technique
1-Single-ended
imbalanced SA
2-Single-ended SA
Wide AND
NOR
Differential
Memory modes
BCAM/SRAM/
Pseudo-TCAM
BCAM/TCAM/ SRAM
BCAM
BCAM
BCAM
a
Area with compact design rules (with waiver on metal routing)
b
Calculated value = 300 ps periphery delay estimation + measured WL
MI N
c
Calculated value assuming measured WL
MI N is 80% of the clock cycle at 0.38 V
89
Table 6.4
CMOS CAM/SRAM comparison with state-of-the-art [©2017 IEEE]
This work
[6]
[81]
[82]
[83]
Technology
28 nm FDSOI
28 nm FDSOI
32 nm
65 nm
0.13
µm
Transistors/cell
6T
6T
11T
10T
9T + Read
Area/cell (µm 2
)
0.197
µm 2 a
0.152
µm 2
–
3.3
20
Array size
128
× 64
64
× 64
(64
× 64)
× 4
128
× 128
128
× 32
Frequency (VDD)
1.56 GHz (0.9 V) b
8.90 MHz (0.38 V) c
370 MHz (1 V)
500 MHz (1 V)
250 MHz (1 V)
Energy/search/bit
(fJ)
0.13 (0.9 V)
0.6 (1 V) 0.41 (0.75V)
1.07 (1 V) 0.3 (0.5 V)
0.77 (1.2V)
1.87 (1 V)
Match-line
technique
1-Single-ended
imbalanced SA
2-Single-ended SA
Wide AND
NOR
Differential
Memory modes
BCAM/SRAM/
Pseudo-TCAM
BCAM/TCAM/ SRAM
BCAM
BCAM
BCAM
a
Area with compact design rules (with waiver on metal routing)
b
Calculated value = 300 ps periphery delay estimation + measured WL
MI N
c
Calculated value assuming measured WL
MI N is 80% of the clock cycle at 0.38 V