90
6 Content-Addressable Memories
to 14.3× over published CAM/SRAMs. The search speed is also improved up
to 3.12× to 6.24×. The implementation is compatible with compact 6T-SRAM
foundry bitcells.
6.4 Associative Memory Architecture
This section presents the design and operation of an associative memory architecture
that can be used in search applications such as pattern matching and neuroinspired computing. In particular, this section focuses on the operation of an
associative memory, which can be implemented using CMOS, FinFET, TFET, or
non-volatile memory technologies. Reports on this subject in literature describe
associative memory implementations either in software for algorithms or emulations
in neuromorphic networks. Most of the research done on hardware implementations of associative memories is oriented towards neuromorphic computing.
Neuromorphic implementations are used for applications such as pattern matching
[84, 85] and approximate computing for power-performance trade-off; examples
of the latter are approximate Floating-Point Unit (FPU) or Special-Purpose Units
(SFUs) using associative memory [86–90]. Associative memories such as ReRAMs
and STTRAMs reported in literature are implemented using non-volatile memories. Non-volatile memory technologies are limited in usage because of the lack
of maturity and compatibility with CMOS in terms of operating voltages and
speed. Software implementations of associative memories are used in algorithms
with hashing methods for lookups, e.g. IP lookups, longest prefix matching, etc.
However, software implementations are compute intensive and cannot be used in
application-specific hardware where area/power needs to be optimized. Associative
memory implementation using CMOS memories provides the best option for using
it as embedded IP in ASICs. This section focuses on extending the SRAM/CAM
presented in the previous section to associative memory architectures.
6.4.1 Associative Memory Architecture with CMOS CAM
Bitcell
In this section we propose a CAM-based low-power and area-efficient associative
memory architecture. As shown in Fig. 6.15 the fundamental idea is to use optimized
comparison logic on match lines of the CAM to find the closest match to the word.
The optimized comparison logic to be integrated with the CMOS CAM is based on
Winner-Take-All (WTA) logic. Figure 6.16 shows a 6T-NOR CAM cell compatible
with this architecture. The bitlines shown on both sides of the cell are shorted in
WTA and used as a single bitline (BL) per column similar to the CMOS ReCSAM
cell introduced in Sect. 6.3, Fig. 6.7. In the proposed architecture words are stored
6 Content-Addressable Memories
to 14.3× over published CAM/SRAMs. The search speed is also improved up
to 3.12× to 6.24×. The implementation is compatible with compact 6T-SRAM
foundry bitcells.
6.4 Associative Memory Architecture
This section presents the design and operation of an associative memory architecture
that can be used in search applications such as pattern matching and neuroinspired computing. In particular, this section focuses on the operation of an
associative memory, which can be implemented using CMOS, FinFET, TFET, or
non-volatile memory technologies. Reports on this subject in literature describe
associative memory implementations either in software for algorithms or emulations
in neuromorphic networks. Most of the research done on hardware implementations of associative memories is oriented towards neuromorphic computing.
Neuromorphic implementations are used for applications such as pattern matching
[84, 85] and approximate computing for power-performance trade-off; examples
of the latter are approximate Floating-Point Unit (FPU) or Special-Purpose Units
(SFUs) using associative memory [86–90]. Associative memories such as ReRAMs
and STTRAMs reported in literature are implemented using non-volatile memories. Non-volatile memory technologies are limited in usage because of the lack
of maturity and compatibility with CMOS in terms of operating voltages and
speed. Software implementations of associative memories are used in algorithms
with hashing methods for lookups, e.g. IP lookups, longest prefix matching, etc.
However, software implementations are compute intensive and cannot be used in
application-specific hardware where area/power needs to be optimized. Associative
memory implementation using CMOS memories provides the best option for using
it as embedded IP in ASICs. This section focuses on extending the SRAM/CAM
presented in the previous section to associative memory architectures.
6.4.1 Associative Memory Architecture with CMOS CAM
Bitcell
In this section we propose a CAM-based low-power and area-efficient associative
memory architecture. As shown in Fig. 6.15 the fundamental idea is to use optimized
comparison logic on match lines of the CAM to find the closest match to the word.
The optimized comparison logic to be integrated with the CMOS CAM is based on
Winner-Take-All (WTA) logic. Figure 6.16 shows a 6T-NOR CAM cell compatible
with this architecture. The bitlines shown on both sides of the cell are shorted in
WTA and used as a single bitline (BL) per column similar to the CMOS ReCSAM
cell introduced in Sect. 6.3, Fig. 6.7. In the proposed architecture words are stored