88
6 Content-Addressable Memories
VDDmin [V]
0
1
2
3
4
5
6
7
0,38 0,39 0,4 0,44 0,49
No. of Chips
0
5
10
15
20
25
0,4 0,5 0,6 0,7 0,8 0,9
VDD [V]
Current [pA]
a.
b.
Fig. 6.13 VDDmin distribution for ten chips and bitcell leakage. (a) VDDmin distribution. (b)
Bitcell Leakage [©2017 IEEE]
0.0
1.0
2.0
3.0
4.0
5.0
0.65
0.7
WLB=0.15V WLB=0.1V
WLB=0.05V WLB=0V
0.0
2.0
4.0
6.0
0.65
0.7
NBL=0V
NBL=0.05V
NBL=0.1V
1.88x
6x
Freq. Imp. Factor
Supply Voltage[V]
Freq. Imp. Factor
Supply Voltage[V]
a.
b.
Fig. 6.14 Assist techniques analysis, (a) WL boosting, (b) negative bitline [©2017 IEEE]
The analysis of the impact of assist techniques for sub-0.8 V, i.e., negative bitline
for write and WL boosting for read is shown in Fig. 6.14. Speed improvements of up
to 1.88× and 6× were measured at sub-0.7 V supply for read and write, respectively.
Table 6.4 presents the comparison of measured results with the state-of-the-art
showing the following energy improvement figures: 4.6× [6], 8.3× [81], 5.9×
[82], and 14.3× [83]. Search speed is also improved compared to the corresponding
references by 4.2× [6], 3.12× [82], 6.24× [83].
6.3.3 Summary
A high-speed 6T-CMOS ReCSAM (Reconfigurable CAM/SRAM) memory architecture with a new energy-efficient sensing technique is proposed through extension
of the TFET ReCSAM design introduced in Sect. 6.2. It is shown that starting
from a new architecture (i.e., TFET/CMOS) and by redesigning the array, the
new principles of design can be applied to the mature CMOS technology and
important benefits can be obtained, see Table 6.4. A test-macro of 8 Kb was
implemented in 28 nm FDSOI CMOS reaching up to 1.56 GHz at 0.9 V with
0.13 fJ/bit energy consumption per search, achieving an improvement of 4.6×
6 Content-Addressable Memories
VDDmin [V]
0
1
2
3
4
5
6
7
0,38 0,39 0,4 0,44 0,49
No. of Chips
0
5
10
15
20
25
0,4 0,5 0,6 0,7 0,8 0,9
VDD [V]
Current [pA]
a.
b.
Fig. 6.13 VDDmin distribution for ten chips and bitcell leakage. (a) VDDmin distribution. (b)
Bitcell Leakage [©2017 IEEE]
0.0
1.0
2.0
3.0
4.0
5.0
0.65
0.7
WLB=0.15V WLB=0.1V
WLB=0.05V WLB=0V
0.0
2.0
4.0
6.0
0.65
0.7
NBL=0V
NBL=0.05V
NBL=0.1V
1.88x
6x
Freq. Imp. Factor
Supply Voltage[V]
Freq. Imp. Factor
Supply Voltage[V]
a.
b.
Fig. 6.14 Assist techniques analysis, (a) WL boosting, (b) negative bitline [©2017 IEEE]
The analysis of the impact of assist techniques for sub-0.8 V, i.e., negative bitline
for write and WL boosting for read is shown in Fig. 6.14. Speed improvements of up
to 1.88× and 6× were measured at sub-0.7 V supply for read and write, respectively.
Table 6.4 presents the comparison of measured results with the state-of-the-art
showing the following energy improvement figures: 4.6× [6], 8.3× [81], 5.9×
[82], and 14.3× [83]. Search speed is also improved compared to the corresponding
references by 4.2× [6], 3.12× [82], 6.24× [83].
6.3.3 Summary
A high-speed 6T-CMOS ReCSAM (Reconfigurable CAM/SRAM) memory architecture with a new energy-efficient sensing technique is proposed through extension
of the TFET ReCSAM design introduced in Sect. 6.2. It is shown that starting
from a new architecture (i.e., TFET/CMOS) and by redesigning the array, the
new principles of design can be applied to the mature CMOS technology and
important benefits can be obtained, see Table 6.4. A test-macro of 8 Kb was
implemented in 28 nm FDSOI CMOS reaching up to 1.56 GHz at 0.9 V with
0.13 fJ/bit energy consumption per search, achieving an improvement of 4.6×