6.3 ReConfigurable CAM Extension to CMOS
83
utilization in a wide variety of applications. Reconfigurability allows runtime
change between SRAM and CAM modes of operation. However, CMOS design
challenges are different due to the bidirectional current flow between source and
drain. Therefore, a new kind of sensing method is proposed, which allows operation
of the design at high speed while maintaining reliability. The proposed memory
supports single-cycle read/write operations and parallel search in all columns.
6.3.1 ReCSAM Architecture
The CMOS ReCSAM architecture is shown in Fig. 6.7, CAM data words are stored
vertically in a column aligned with bitlines and orthogonal to wordlines. In CAM
mode, a single-bitline configuration is used by shorting BL and BLB in the IO
logic using a configuration bit (cam_mode). In this architecture, the cell array is
optimized and dynamic reconfigurability is introduced with additional digital logic
implemented in wordline and bitline drivers. The bitcell is using the sizing of the
28 nm FDSOI foundry library bitcell with modifications in Metal-2 and Metal-3
connections to include dual wordlines and vertical ground routing. The area of the
implemented bitcell is 0.277 µm 2 with logic design rules; with compact-memory
rules the area would be reduced to 0.197 µm 2 . The different operation modes of this
architecture are described in the following subsections.
6.3.1.1 Binary CAM (BCAM)
Data search is performed with the bitlines pulled up using the virtual ground “vs” of
the bitcell working as match line and the wordlines wl1 and wl2 as search data lines.
This approach improves the stability of the bitcell, reducing energy consumption and
VSS
RD_EN
MEM
Cell
MEM
Cell
MEM
Cell
bl
Vdd
vd
vs
bl
blb
wl1
wl2
Imbalanced
single-ended SA
cam_mode
blb
Data Output
(SRAM read/
CAM search)
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
c
i
g
o
l
L
W
+
s
r
e
v
i
r
D
L
W
WL Drivers + WL logic
SRAM WORD
IO Logic
PREDEC
CAM WORD
•Vertical CAM words
•Dual wordlines
•Data dependent WL’s
•Conventional SRAM mode
Data out [SRAM/CAM]
Control/data/address
Single Column, sensing technique and bitcell
BL
BLB
BL
BLB
Fig. 6.7 Memory organization [©2017 IEEE]
83
utilization in a wide variety of applications. Reconfigurability allows runtime
change between SRAM and CAM modes of operation. However, CMOS design
challenges are different due to the bidirectional current flow between source and
drain. Therefore, a new kind of sensing method is proposed, which allows operation
of the design at high speed while maintaining reliability. The proposed memory
supports single-cycle read/write operations and parallel search in all columns.
6.3.1 ReCSAM Architecture
The CMOS ReCSAM architecture is shown in Fig. 6.7, CAM data words are stored
vertically in a column aligned with bitlines and orthogonal to wordlines. In CAM
mode, a single-bitline configuration is used by shorting BL and BLB in the IO
logic using a configuration bit (cam_mode). In this architecture, the cell array is
optimized and dynamic reconfigurability is introduced with additional digital logic
implemented in wordline and bitline drivers. The bitcell is using the sizing of the
28 nm FDSOI foundry library bitcell with modifications in Metal-2 and Metal-3
connections to include dual wordlines and vertical ground routing. The area of the
implemented bitcell is 0.277 µm 2 with logic design rules; with compact-memory
rules the area would be reduced to 0.197 µm 2 . The different operation modes of this
architecture are described in the following subsections.
6.3.1.1 Binary CAM (BCAM)
Data search is performed with the bitlines pulled up using the virtual ground “vs” of
the bitcell working as match line and the wordlines wl1 and wl2 as search data lines.
This approach improves the stability of the bitcell, reducing energy consumption and
VSS
RD_EN
MEM
Cell
MEM
Cell
MEM
Cell
bl
Vdd
vd
vs
bl
blb
wl1
wl2
Imbalanced
single-ended SA
cam_mode
blb
Data Output
(SRAM read/
CAM search)
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
c
i
g
o
l
L
W
+
s
r
e
v
i
r
D
L
W
WL Drivers + WL logic
SRAM WORD
IO Logic
PREDEC
CAM WORD
•Vertical CAM words
•Dual wordlines
•Data dependent WL’s
•Conventional SRAM mode
Data out [SRAM/CAM]
Control/data/address
Single Column, sensing technique and bitcell
BL
BLB
BL
BLB
Fig. 6.7 Memory organization [©2017 IEEE]