82
6 Content-Addressable Memories
ended sensing and 6T-SRAM differential read, respectively. E W RI T E is the energy
consumed during write operation. I LEAK in active mode is the total leakage in the
bitcell array and periphery operating as an SRAM with dynamic power gating with
only 25% of the drivers active.
In estimating E READ for CAM mode full array parallel search is considered,
while for SRAM mode, single-word read is considered. Therefore, energy per bit
is 17× lower for CAM mode in comparison to SRAM mode. E W RI T E is estimated
considering single-word write, i.e., for a single column. Additional power-saving
techniques are used for IO logic; for SRAM mode only 16 drivers, i.e. eight rows, are
active with others power gated, while CAM mode needs all drivers active. Therefore,
active-mode leakage is up to 87% less for SRAM mode in comparison to CAM
mode. For comparison purposes, reports from literature with low-leakage Ternary
CAM (TCAM), CAM, and SRAMs are also shown in Table 6.3. It can be seen
that the standby power of the presented design is 10 6 × less in comparison to other
SRAM, CAM, and TCAM cells. The cell size is 3.12× larger than the standard
6T-CMOS SRAM cell but 5.4× smaller than the ultra-low leakage SRAM cell [8];
CAM/TCAM cells reported in literature are even bigger in size. Evaluated static
noise margins at 1 V supply are 120 mV and 200 mV for write and read, respectively.
6.2.4 Summary
An ultra-low leakage reconfigurable TFET CAM/SRAM (ReCSAM), which can
work as CAM and/or as SRAM has been presented in this section. The design is
useful in order to efficiently utilize the available embedded memory for a wide
range of applications. Less than 5fA/bit memory array leakage current is achieved
at 1 V supply voltage, an improvement of up to 10 6 × compared with state-of-theart CMOS SRAM and CAM bitcells. The proposed CAM architecture supports
voltage scaling and allows application of performance boosting techniques without
impacting cell leakage. The minimum write access pulse for CAM and SRAM
modes is evaluated at 1.37 ns at 1 V supply voltage; for read the evaluated access
pulse is 1.39 ns and 1.03 ns at 1 V for CAM and SRAM modes, respectively. The
design supports different configurations, such as variable tag size, variable word size
and can operate as a combination of CAM and SRAM. These configurations can be
chosen at implementation time or can be made programmable to dynamically adjust
them as required during runtime.
6.3 ReConfigurable CAM Extension to CMOS
The CMOS ReCSAM bitcell is designed using similar concepts as the 9T-TFET
ReCSAM bitcell presented in Sect. 6.2 such as dual wordlines and the bitline used
as match line. The proposed CMOS ReCSAM design is meant for efficient memory
6 Content-Addressable Memories
ended sensing and 6T-SRAM differential read, respectively. E W RI T E is the energy
consumed during write operation. I LEAK in active mode is the total leakage in the
bitcell array and periphery operating as an SRAM with dynamic power gating with
only 25% of the drivers active.
In estimating E READ for CAM mode full array parallel search is considered,
while for SRAM mode, single-word read is considered. Therefore, energy per bit
is 17× lower for CAM mode in comparison to SRAM mode. E W RI T E is estimated
considering single-word write, i.e., for a single column. Additional power-saving
techniques are used for IO logic; for SRAM mode only 16 drivers, i.e. eight rows, are
active with others power gated, while CAM mode needs all drivers active. Therefore,
active-mode leakage is up to 87% less for SRAM mode in comparison to CAM
mode. For comparison purposes, reports from literature with low-leakage Ternary
CAM (TCAM), CAM, and SRAMs are also shown in Table 6.3. It can be seen
that the standby power of the presented design is 10 6 × less in comparison to other
SRAM, CAM, and TCAM cells. The cell size is 3.12× larger than the standard
6T-CMOS SRAM cell but 5.4× smaller than the ultra-low leakage SRAM cell [8];
CAM/TCAM cells reported in literature are even bigger in size. Evaluated static
noise margins at 1 V supply are 120 mV and 200 mV for write and read, respectively.
6.2.4 Summary
An ultra-low leakage reconfigurable TFET CAM/SRAM (ReCSAM), which can
work as CAM and/or as SRAM has been presented in this section. The design is
useful in order to efficiently utilize the available embedded memory for a wide
range of applications. Less than 5fA/bit memory array leakage current is achieved
at 1 V supply voltage, an improvement of up to 10 6 × compared with state-of-theart CMOS SRAM and CAM bitcells. The proposed CAM architecture supports
voltage scaling and allows application of performance boosting techniques without
impacting cell leakage. The minimum write access pulse for CAM and SRAM
modes is evaluated at 1.37 ns at 1 V supply voltage; for read the evaluated access
pulse is 1.39 ns and 1.03 ns at 1 V for CAM and SRAM modes, respectively. The
design supports different configurations, such as variable tag size, variable word size
and can operate as a combination of CAM and SRAM. These configurations can be
chosen at implementation time or can be made programmable to dynamically adjust
them as required during runtime.
6.3 ReConfigurable CAM Extension to CMOS
The CMOS ReCSAM bitcell is designed using similar concepts as the 9T-TFET
ReCSAM bitcell presented in Sect. 6.2 such as dual wordlines and the bitline used
as match line. The proposed CMOS ReCSAM design is meant for efficient memory