74
6 Content-Addressable Memories
A possible solution is to design a Reconfigurable CAM/SRAM (ReCSAM),
which can operate either as CAM and/or as SRAM depending on the application’s
needs. Sharing the memory array between CAM and SRAM optimizes the overall
memory footprint by maximizing the average memory utilization and hence reduces
total area and power while maintaining high speed of operation. For example, in
applications which do not require a big L2 cache on a SoC as in [73], CAMs
can be used as SRAM buffer or as register file. Sharing memory resources is an
important aspect as the total memory capacity has to be increased to meet worstcase application requirements resulting in area overhead and leakage; however, few
recent reports in literature focused on the reduction of CAM standby power [77, 78].
Techniques like fine-grain power gating, smaller match line, and pipelined search
were implemented and benchmarked. CAM leakage power reported in literature
is in the range of nA/bit [77] for CMOS technology. In order to further reduce
leakage, other than CMOS technologies are also explored by researchers. In [78], the
authors reported leakage in the range of pA/bit in CMOS with non-volatile elements
(magnetic tunnel junctions) and hierarchal power gating.
Another aspect of CAM design is optimizing them for approximate-search,
which allows to find the closest match of data in place of exact match. Such
associative search in memories is useful for applications such as pattern search and
face recognition.
This chapter analyzes the applicability of TFETs to content-addressable memories (CAMs) and presents ways to optimize the memory footprint in systems
for LSTP applications using reconfigurability for longer battery life and/or energy
harvesting.
In Sect. 6.2 we propose a TFET/CMOS hybrid reconfigurable CAM (ReCSAM),
which can operate either as CAM and/or as SRAM depending on the application
requirements [79]. TFET devices considered in this work are compatible with
CMOS processes for fabrication. This allows the implementation of heterogeneous
cores in a single FDSOI-CMOS process using both TFET and CMOS devices for
arithmetic logic units and memories.
Also presented in this chapter, Sect. 6.3, is an extension of the TFET/CMOS
CAM concept to a CMOS-only reconfigurable CAM/SRAM (ReCSAM) architecture based on the 6T-CMOS bitcell operating either as CAM and/or as SRAM
depending on the application requirements [66] showing the advantages that can
already be obtained on a mature technology (CMOS) having as a starting point
the new design concepts inspired by an emerging technology (TFET) or by the
hybridization of CMOS with TFET.
An extension of the ReCSAM to an associative memory architecture is proposed
in Sect. 6.4. CMOS-only and TFET/CMOS hybrid architectures are proposed using
6T-CMOS and 8T-TFET bitcells, respectively. Section 6.5 describes Ternary CAM
(TCAM) based on a novel TFET multi-bit latch using the NDR property of TFETs.
6 Content-Addressable Memories
A possible solution is to design a Reconfigurable CAM/SRAM (ReCSAM),
which can operate either as CAM and/or as SRAM depending on the application’s
needs. Sharing the memory array between CAM and SRAM optimizes the overall
memory footprint by maximizing the average memory utilization and hence reduces
total area and power while maintaining high speed of operation. For example, in
applications which do not require a big L2 cache on a SoC as in [73], CAMs
can be used as SRAM buffer or as register file. Sharing memory resources is an
important aspect as the total memory capacity has to be increased to meet worstcase application requirements resulting in area overhead and leakage; however, few
recent reports in literature focused on the reduction of CAM standby power [77, 78].
Techniques like fine-grain power gating, smaller match line, and pipelined search
were implemented and benchmarked. CAM leakage power reported in literature
is in the range of nA/bit [77] for CMOS technology. In order to further reduce
leakage, other than CMOS technologies are also explored by researchers. In [78], the
authors reported leakage in the range of pA/bit in CMOS with non-volatile elements
(magnetic tunnel junctions) and hierarchal power gating.
Another aspect of CAM design is optimizing them for approximate-search,
which allows to find the closest match of data in place of exact match. Such
associative search in memories is useful for applications such as pattern search and
face recognition.
This chapter analyzes the applicability of TFETs to content-addressable memories (CAMs) and presents ways to optimize the memory footprint in systems
for LSTP applications using reconfigurability for longer battery life and/or energy
harvesting.
In Sect. 6.2 we propose a TFET/CMOS hybrid reconfigurable CAM (ReCSAM),
which can operate either as CAM and/or as SRAM depending on the application
requirements [79]. TFET devices considered in this work are compatible with
CMOS processes for fabrication. This allows the implementation of heterogeneous
cores in a single FDSOI-CMOS process using both TFET and CMOS devices for
arithmetic logic units and memories.
Also presented in this chapter, Sect. 6.3, is an extension of the TFET/CMOS
CAM concept to a CMOS-only reconfigurable CAM/SRAM (ReCSAM) architecture based on the 6T-CMOS bitcell operating either as CAM and/or as SRAM
depending on the application requirements [66] showing the advantages that can
already be obtained on a mature technology (CMOS) having as a starting point
the new design concepts inspired by an emerging technology (TFET) or by the
hybridization of CMOS with TFET.
An extension of the ReCSAM to an associative memory architecture is proposed
in Sect. 6.4. CMOS-only and TFET/CMOS hybrid architectures are proposed using
6T-CMOS and 8T-TFET bitcells, respectively. Section 6.5 describes Ternary CAM
(TCAM) based on a novel TFET multi-bit latch using the NDR property of TFETs.