Chapter 6
Content-Addressable Memories
6.1 Introduction
Content-addressable memories (CAMs) differentiate themselves from other memories as information is accessed by data instead of physical location. This makes
CAMs popular in high-speed hardware-based search operations, such as look-up
tables, data compression, image processing, register renaming [72], look-up buffers,
and as highly associative caches in processors. However, using CAMs in systems
efficiently is a challenge due to its high area cost and power dissipation. Since the
parallel search operation is performed in the memory, optimization of speed and
energy per search is crucial for an efficient CAM architecture. Another challenge
for CAMs is the increasing leakage with every new technology node. Therefore,
minimization of area and power consumption of CAMs for processor-based SoCs
becomes an important design challenge.
In order to use CAMs as cache memory, it is important to optimize them for
the specifics of each application. The best cache configuration depends mainly
on the application requirements and design constraints leading to diverse cache
architectures found in different processors. Therefore, it is difficult to find a single
cache architecture fulfilling requirements of all applications. Examples include
flexible architectures such as FPGAs with built-in ASIC blocks [73] or ARM
cores with a large L2 (512 KB) cache, which needs a CAM for storing tags. ASIC
and FPGA-based cache designs are proposed in [74–76], which can be configured
dynamically to change the behavior in terms of associativity or mode of operation,
cache or scratchpad, depending on the application requirements. However, while
FPGA-based CAMs [76] have the advantage of flexibility, their performance and
use-cases are limited. CAMs [74, 75] implemented in ASICs, on the other hand, are
better optimized for area and speed but they have limited flexibility in comparison
to the FPGA-based ones. Today, there is a need for designing flexible ASICimplemented CAMs that can provide close-to-optimum performance for a large
variety of applications.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_6
73
Content-Addressable Memories
6.1 Introduction
Content-addressable memories (CAMs) differentiate themselves from other memories as information is accessed by data instead of physical location. This makes
CAMs popular in high-speed hardware-based search operations, such as look-up
tables, data compression, image processing, register renaming [72], look-up buffers,
and as highly associative caches in processors. However, using CAMs in systems
efficiently is a challenge due to its high area cost and power dissipation. Since the
parallel search operation is performed in the memory, optimization of speed and
energy per search is crucial for an efficient CAM architecture. Another challenge
for CAMs is the increasing leakage with every new technology node. Therefore,
minimization of area and power consumption of CAMs for processor-based SoCs
becomes an important design challenge.
In order to use CAMs as cache memory, it is important to optimize them for
the specifics of each application. The best cache configuration depends mainly
on the application requirements and design constraints leading to diverse cache
architectures found in different processors. Therefore, it is difficult to find a single
cache architecture fulfilling requirements of all applications. Examples include
flexible architectures such as FPGAs with built-in ASIC blocks [73] or ARM
cores with a large L2 (512 KB) cache, which needs a CAM for storing tags. ASIC
and FPGA-based cache designs are proposed in [74–76], which can be configured
dynamically to change the behavior in terms of associativity or mode of operation,
cache or scratchpad, depending on the application requirements. However, while
FPGA-based CAMs [76] have the advantage of flexibility, their performance and
use-cases are limited. CAMs [74, 75] implemented in ASICs, on the other hand, are
better optimized for area and speed but they have limited flexibility in comparison
to the FPGA-based ones. Today, there is a need for designing flexible ASICimplemented CAMs that can provide close-to-optimum performance for a large
variety of applications.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_6
73