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5 TFET NDR Flip-Flop
The performance in terms of speed and power was evaluated and compared with
published flip-flop designs using TFET, MOSFET, and FinFET devices. Leakage
power reduction from 4 to 7 orders of magnitude compared to MOSFET and FinFET
implementations was achieved. Dynamic power is reduced from 3 to 5 orders of
magnitude in comparison to MOSFET and FinFET MSFF implementations. Maximum operating frequency for the proposed design is 23× higher than MOSFET
and LSTP-FinFET implementations but comparable to that of the HP-FinFET MS
flip-flop while having 10 7 × less leakage.
5 TFET NDR Flip-Flop
The performance in terms of speed and power was evaluated and compared with
published flip-flop designs using TFET, MOSFET, and FinFET devices. Leakage
power reduction from 4 to 7 orders of magnitude compared to MOSFET and FinFET
implementations was achieved. Dynamic power is reduced from 3 to 5 orders of
magnitude in comparison to MOSFET and FinFET MSFF implementations. Maximum operating frequency for the proposed design is 23× higher than MOSFET
and LSTP-FinFET implementations but comparable to that of the HP-FinFET MS
flip-flop while having 10 7 × less leakage.