5.5 Summary
71
1,00
10,00
100,00
1 000,00
MS
TGFF
C2MOSFF
SDFF
SAFF
MSAFF
DFF
MOSFET VDD=0.8
MOSFET VDD=0.5
FinFET VDD=0.8
FinFET VDD=0.5
HTFET_FF VDD=0.5
HTFET_FF VDD=0.3
TFET_FF VDD=0.5
TFET_FF VDD=0.3
CMOS_FF VDD=0.5
FinFET_FF VDD=0.5
FinFET_HP_FF VDD=0.3
T
l
a
c
i
t
i
r
C
]
s
p
[
simulated
MSFF
values estimated from graphs in literature
Fig. 5.16 Comparison—T Critical for different designs [©2016 IEEE]
in region II, see Chap. 2, Fig. 2.9. The enumerated features of our TFET device
and proposed design result in the lowest static power consumption among all the
implementations. In [70] only the leakage energy is reported, which is dependent on
the timing window considered for measurement. Thus, an absolute comparison of
static power consumption with [70] is not presented.
5.5 Summary
This chapter demonstrated the superiority of TFETs for implementing flip-flops;
TFET’s NDR and unidirectionality features were used to design a novel 12T-TFET
MSFF architecture optimized for low cost and low power. The proposed flip-flop
design uses 12/14 transistors (without clock buffered locally) and represents a
promising architecture for near-threshold or subthreshold computing. The building
blocks of the 12T-TFET flip-flop are the NDR-based 2T-TFET latch for data
storage and 2T-TFET tri-state inverter taking advantage of unidirectionality and
using CLK/CLKN as inverter supplies and latch biases. The flip-flop operates with
ultra-low leakage current (<3 fA) for supply voltages up to 0.6 V. The TFET flipflop supports voltage scaling and works from 0.6 V down to 0.3 V supply voltage.
71
1,00
10,00
100,00
1 000,00
MS
TGFF
C2MOSFF
SDFF
SAFF
MSAFF
DFF
MOSFET VDD=0.8
MOSFET VDD=0.5
FinFET VDD=0.8
FinFET VDD=0.5
HTFET_FF VDD=0.5
HTFET_FF VDD=0.3
TFET_FF VDD=0.5
TFET_FF VDD=0.3
CMOS_FF VDD=0.5
FinFET_FF VDD=0.5
FinFET_HP_FF VDD=0.3
T
l
a
c
i
t
i
r
C
]
s
p
[
simulated
MSFF
values estimated from graphs in literature
Fig. 5.16 Comparison—T Critical for different designs [©2016 IEEE]
in region II, see Chap. 2, Fig. 2.9. The enumerated features of our TFET device
and proposed design result in the lowest static power consumption among all the
implementations. In [70] only the leakage energy is reported, which is dependent on
the timing window considered for measurement. Thus, an absolute comparison of
static power consumption with [70] is not presented.
5.5 Summary
This chapter demonstrated the superiority of TFETs for implementing flip-flops;
TFET’s NDR and unidirectionality features were used to design a novel 12T-TFET
MSFF architecture optimized for low cost and low power. The proposed flip-flop
design uses 12/14 transistors (without clock buffered locally) and represents a
promising architecture for near-threshold or subthreshold computing. The building
blocks of the 12T-TFET flip-flop are the NDR-based 2T-TFET latch for data
storage and 2T-TFET tri-state inverter taking advantage of unidirectionality and
using CLK/CLKN as inverter supplies and latch biases. The flip-flop operates with
ultra-low leakage current (<3 fA) for supply voltages up to 0.6 V. The TFET flipflop supports voltage scaling and works from 0.6 V down to 0.3 V supply voltage.