70
5 TFET NDR Flip-Flop
1,00
10,00
100,00
1 000,00
MS
TGFF
C2MOSFF
SDFF
SAFF
MSAFF
DFF
MOSFET VDD=0.8
MOSFET VDD=0.5
FinFET VDD=0.8
FinFET VDD=0.5
HTFET_FF VDD=0.5
HTFET_FF VDD=0.3
TFET_FF VDD=0.5
TFET_FF VDD=0.3
CMOS_FF VDD=0.5
FinFET_FF VDD=0.5
FinFET_HP_FF VDD=0.3
T
Q
2
P
C
]
s
p
[
simulated
MSFF
values estimated from graphs in literature
Fig. 5.15 Comparison—T CP 2Q for different designs [©2016 IEEE]
5.4.3 Minimum Clock Period Required T Critical
T Critical is defined as T Setup + T CP 2Q : this represents the theoretical limit for
the minimum possible clock period for proper flip-flop operation. As shown in
Fig. 5.16, the 12T-TFET MSFF has a T Critical similar to that of the FinFET and
heterojunction-TFET flip-flops at 0.8 V and 0.5 V, respectively.
5.4.4 Leakage
The reduced leakage power in the proposed design in comparison to CMOS and
FinFET FFs is due to the ultra-low OFF current (region II, see Chap. 2, Fig. 2.9) of
the TFET (I OF F ≈ 10 −14 A/µm). Significant improvement in terms of leakage
also in comparison to other TFET flip-flop designs [70] is due to an optimized
TFET device for OFF current and the flip-flop architecture, which ensures TFET
devices are never in a high parasitic current (region III, see Chap. 2, Fig. 2.9)
operating condition by taking advantage of the NDR property. The focus for TFETs
in [70] is to increase I ON for better performance at the cost of leakage (I OF F ≈
10 −9 A/µm). In our design more than half of the TFETs are always biased with
reverse V DS where I OF F is at its minimum and is independent of V GS operating
5 TFET NDR Flip-Flop
1,00
10,00
100,00
1 000,00
MS
TGFF
C2MOSFF
SDFF
SAFF
MSAFF
DFF
MOSFET VDD=0.8
MOSFET VDD=0.5
FinFET VDD=0.8
FinFET VDD=0.5
HTFET_FF VDD=0.5
HTFET_FF VDD=0.3
TFET_FF VDD=0.5
TFET_FF VDD=0.3
CMOS_FF VDD=0.5
FinFET_FF VDD=0.5
FinFET_HP_FF VDD=0.3
T
Q
2
P
C
]
s
p
[
simulated
MSFF
values estimated from graphs in literature
Fig. 5.15 Comparison—T CP 2Q for different designs [©2016 IEEE]
5.4.3 Minimum Clock Period Required T Critical
T Critical is defined as T Setup + T CP 2Q : this represents the theoretical limit for
the minimum possible clock period for proper flip-flop operation. As shown in
Fig. 5.16, the 12T-TFET MSFF has a T Critical similar to that of the FinFET and
heterojunction-TFET flip-flops at 0.8 V and 0.5 V, respectively.
5.4.4 Leakage
The reduced leakage power in the proposed design in comparison to CMOS and
FinFET FFs is due to the ultra-low OFF current (region II, see Chap. 2, Fig. 2.9) of
the TFET (I OF F ≈ 10 −14 A/µm). Significant improvement in terms of leakage
also in comparison to other TFET flip-flop designs [70] is due to an optimized
TFET device for OFF current and the flip-flop architecture, which ensures TFET
devices are never in a high parasitic current (region III, see Chap. 2, Fig. 2.9)
operating condition by taking advantage of the NDR property. The focus for TFETs
in [70] is to increase I ON for better performance at the cost of leakage (I OF F ≈
10 −9 A/µm). In our design more than half of the TFETs are always biased with
reverse V DS where I OF F is at its minimum and is independent of V GS operating