66
5 TFET NDR Flip-Flop
0,3
0,4
0,5
0,6
CMOS FF
FinFET FF
TFET-FF
FinFET FF-HP
Supply Voltage [V]
Leakage Power [pW]
10 -4
10 -2
10 0
10 2
10 4
Fig. 5.9 12T-TFET FF comparison with LP-CMOS and FinFET FF’s: leakage power vs. supply
voltage [©2016 IEEE]
0,01
0,10
1,00
10,00
1,00
10,00
100,00
0,3
0,4
0,5
0,6
CMOS FF
FinFET FF
FinFET FF-HP
TFET-FF
Supply Voltage [V]
Dynamic Power [nW]
Dynamic Power [pW]
10 0
10 1
10 2
10 3
Fig. 5.10 12T-TFET FF comparison with LP-CMOS and FinFET FF’s: dynamic power consumption vs. supply voltage [©2016 IEEE]
5.3.3 Performance
Usually, the flip-flop performance is evaluated in terms of T Setup and T CP 2Q .
Figure 5.11 shows the T Setup requirement for the proposed TFET, CMOS, and
FinFETs (LSTP and HP) MSFF designs. It should be noted that the proposed TFET
design is faster than that of CMOS and FinFET-LSTP for a supply voltage range of
0.3–0.6 V. However, the setup requirement is almost similar to that of FinFET-HP,
which is the fastest overall but also the most power consuming. At 0.3 V supply
T Setup of the TFET design is 14.6× and 56× lower in comparison to the CMOS
and FinFET-LSTP designs, respectively. However, the T Setup is still 3.75× larger
than that of the FinFET-HP MSFF at 0.3 V supply voltage.