64
5 TFET NDR Flip-Flop
CLKN
CLK
CLKN
CLK
CLKN
CLK
CLKN
CLK
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
D
Q !
CLKN
CLK
CLKN
Tri-State Inverter
(I1)
VDD
Latch
(L1)
CLK
Tri-State Inverter
(I2)
O/P Driver-1
Q0
Q1
VDD
GND
Q !
Q
O/P Driver-2
M 0
M 1
M 2
M 3
M 4
M 5
M 6
M 7
M 8
M 9
VDD
Latch
(L2)
Fig. 5.7 Proposed 12T (14T with O/P driver-2) TFET-FF design [©2016 IEEE]
5.3.1 Flip-Flop Operation
The principle of operation of the flip-flop in Fig. 5.7 is as follows. When CLK is low
D is complemented by inverter I1 (M0/M1) to Q0, which is the input to I2 (M4/M5);
the master latch L1 (M2/M3) and inverter I2 (M4/M5) connected to Q1 are tri-state
when CLK is low; therefore, the Q1 value is preserved by slave latch L2 (M6/M7)
and outputs Q ! and Q are driven by output drivers OP Driver 1 and 2. When CLK
is high, input inverter I1 is in tri-state and master latch L1 is preserving the value
on Q0 driving Q1 using inverter I2. During this period slave latch L2 is in tri-state.
The waveforms on the flip-flop inputs, output, and internal nodes for data and clock
transitions are shown in Fig. 5.8.
The 12T-TFET MSFF has the following advantages in comparison to conventional flip-flop designs: (1) at any given point in time, half of the TFETs in the
flip-flop are in reverse bias condition (negative and positive V DS for NTFETs and
PTFETs, respectively) resulting in extremely low leakage for supply voltages up
to 0.6 V (<3 fA/flip-flop); (2) there is neither feedback nor inverter delay within
the latch, resulting in setup time (T Setup ) and CLK-to-Q delay (T CP 2Q ) reduction,
especially for low-voltage operation where inverter delays are large; (3) the total
number of transistors is almost half of the conventional master-slave flip-flop
resulting in reduced area. Due to the above-mentioned advantages, the performance
of the 12T-TFET MSFF in terms of speed and power is better in comparison to
CMOS, FinFET, and other TFET flip-flops reported in literature.
5 TFET NDR Flip-Flop
CLKN
CLK
CLKN
CLK
CLKN
CLK
CLKN
CLK
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
D
Q !
CLKN
CLK
CLKN
Tri-State Inverter
(I1)
VDD
Latch
(L1)
CLK
Tri-State Inverter
(I2)
O/P Driver-1
Q0
Q1
VDD
GND
Q !
Q
O/P Driver-2
M 0
M 1
M 2
M 3
M 4
M 5
M 6
M 7
M 8
M 9
VDD
Latch
(L2)
Fig. 5.7 Proposed 12T (14T with O/P driver-2) TFET-FF design [©2016 IEEE]
5.3.1 Flip-Flop Operation
The principle of operation of the flip-flop in Fig. 5.7 is as follows. When CLK is low
D is complemented by inverter I1 (M0/M1) to Q0, which is the input to I2 (M4/M5);
the master latch L1 (M2/M3) and inverter I2 (M4/M5) connected to Q1 are tri-state
when CLK is low; therefore, the Q1 value is preserved by slave latch L2 (M6/M7)
and outputs Q ! and Q are driven by output drivers OP Driver 1 and 2. When CLK
is high, input inverter I1 is in tri-state and master latch L1 is preserving the value
on Q0 driving Q1 using inverter I2. During this period slave latch L2 is in tri-state.
The waveforms on the flip-flop inputs, output, and internal nodes for data and clock
transitions are shown in Fig. 5.8.
The 12T-TFET MSFF has the following advantages in comparison to conventional flip-flop designs: (1) at any given point in time, half of the TFETs in the
flip-flop are in reverse bias condition (negative and positive V DS for NTFETs and
PTFETs, respectively) resulting in extremely low leakage for supply voltages up
to 0.6 V (<3 fA/flip-flop); (2) there is neither feedback nor inverter delay within
the latch, resulting in setup time (T Setup ) and CLK-to-Q delay (T CP 2Q ) reduction,
especially for low-voltage operation where inverter delays are large; (3) the total
number of transistors is almost half of the conventional master-slave flip-flop
resulting in reduced area. Due to the above-mentioned advantages, the performance
of the 12T-TFET MSFF in terms of speed and power is better in comparison to
CMOS, FinFET, and other TFET flip-flops reported in literature.