5.3 12T-TFET Master-Slave Flip-Flop (MSFF) Design
63
a.
b.
Fig. 5.6 TFET pseudo-static flip-flop [©2013 IEEE]
of TFET devices used in the flip-flop architectures described in [70] should be
increased to a positive value for NTFET and negative value for PTFET at the cost
of degraded performance of flip-flops.
5.3 12T-TFET Master-Slave Flip-Flop (MSFF) Design
We propose a new TFET-FF design [71] that does not suffer from the issues of
the aforementioned designs using a 2T-TFET latch and a 2T-TFET tri-state inverter
as shown in Fig. 5.7; the unidirectional property of TFETs allows implementation
of the tri-state inverter by using only two transistors. The input (D) is connected
to the input of tri-state inverter (I1) consisting of M0 (PTFET) and M1 (NTFET).
When the clock (CLK) is low, M0 and M1 work as an inverter. When CLK is high,
inverter I1 is in tri-state because M0 and M1 have reverse-biased V GS . Similarly,
the other inverter I2 (M4 and M5) is in tri-state when CLK is low and works as
inverter when CLK is high. Master and slave latches are implemented using the
NDR property of TFETs [14]. The operation of the NDR-based latch is similar to
that of the SRAM latch shown in Fig. 3.19 with gate bias voltages replaced by CLK
and CLKN signals in order to implement a tri-state latch. Output drivers are used to
isolate the internal storage latch from the fan-out. The proposed design implements
flip-flops with inverted output using 12-TFETs and with non-inverted output using
14-TFETs.
63
a.
b.
Fig. 5.6 TFET pseudo-static flip-flop [©2013 IEEE]
of TFET devices used in the flip-flop architectures described in [70] should be
increased to a positive value for NTFET and negative value for PTFET at the cost
of degraded performance of flip-flops.
5.3 12T-TFET Master-Slave Flip-Flop (MSFF) Design
We propose a new TFET-FF design [71] that does not suffer from the issues of
the aforementioned designs using a 2T-TFET latch and a 2T-TFET tri-state inverter
as shown in Fig. 5.7; the unidirectional property of TFETs allows implementation
of the tri-state inverter by using only two transistors. The input (D) is connected
to the input of tri-state inverter (I1) consisting of M0 (PTFET) and M1 (NTFET).
When the clock (CLK) is low, M0 and M1 work as an inverter. When CLK is high,
inverter I1 is in tri-state because M0 and M1 have reverse-biased V GS . Similarly,
the other inverter I2 (M4 and M5) is in tri-state when CLK is low and works as
inverter when CLK is high. Master and slave latches are implemented using the
NDR property of TFETs [14]. The operation of the NDR-based latch is similar to
that of the SRAM latch shown in Fig. 3.19 with gate bias voltages replaced by CLK
and CLKN signals in order to implement a tri-state latch. Output drivers are used to
isolate the internal storage latch from the fan-out. The proposed design implements
flip-flops with inverted output using 12-TFETs and with non-inverted output using
14-TFETs.