Chapter 5
TFET NDR Flip-Flop
5.1 Introduction
Cost and power efficiency are an important aspect for applications such as Internetof-Things (IoT) and Wireless-Sensor Nodes (WSN). In SoCs optimized for these
specification, key focus is put on SRAMs and flip-flops as they are the main
contributors to area, energy, and leakage. Flip-flops in particular are critical
components for synchronous logic and microprocessor-based systems where they
are used as pipeline registers, register files, and data-buffers. These systems are often
used in applications, which may run on energy scavenging/small batteries requiring
low-voltage operation. In IoT applications a small form factor is important as even
for a low- to medium-performance microprocessor more than 1000 flip-flops are
required; therefore, optimizing area of flip-flops is an important consideration for
IoT SoCs.
Currently the majority of digital systems are CMOS based, therefore, CMOS
flip-flops are well explored for power and performance optimization [67–69].
Recent flip-flops implemented in other-than CMOS technologies, such as TFET
flip-flops, [70], are designed similarly to the CMOS ones. These technologies
could have advantages over CMOS; the TFET is one of the promising alternatives
to explore for low-voltage and low-power flip-flop designs. However, due to the
unidirectional property of TFETs, their higher drain capacitance and non-saturating
I D − V DS characteristics, standard flip-flop architectures face major performance
constraints. The above-mentioned drawbacks limit the use of TFET-based flip-flops.
This necessitates the investigation of alternative TFET circuit architectures in order
to mitigate the pitfalls and take full advantage of the unique TFET properties for
optimal flip-flop design.
This chapter investigates ultra-compact low-voltage flip-flop design using SiTFETs for ULP applications requiring long battery life while providing good
performance. A summary of the area and power efficiency of the existing CMOS
and TFET circuit architectures is presented in Sect. 5.2.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_5
59
TFET NDR Flip-Flop
5.1 Introduction
Cost and power efficiency are an important aspect for applications such as Internetof-Things (IoT) and Wireless-Sensor Nodes (WSN). In SoCs optimized for these
specification, key focus is put on SRAMs and flip-flops as they are the main
contributors to area, energy, and leakage. Flip-flops in particular are critical
components for synchronous logic and microprocessor-based systems where they
are used as pipeline registers, register files, and data-buffers. These systems are often
used in applications, which may run on energy scavenging/small batteries requiring
low-voltage operation. In IoT applications a small form factor is important as even
for a low- to medium-performance microprocessor more than 1000 flip-flops are
required; therefore, optimizing area of flip-flops is an important consideration for
IoT SoCs.
Currently the majority of digital systems are CMOS based, therefore, CMOS
flip-flops are well explored for power and performance optimization [67–69].
Recent flip-flops implemented in other-than CMOS technologies, such as TFET
flip-flops, [70], are designed similarly to the CMOS ones. These technologies
could have advantages over CMOS; the TFET is one of the promising alternatives
to explore for low-voltage and low-power flip-flop designs. However, due to the
unidirectional property of TFETs, their higher drain capacitance and non-saturating
I D − V DS characteristics, standard flip-flop architectures face major performance
constraints. The above-mentioned drawbacks limit the use of TFET-based flip-flops.
This necessitates the investigation of alternative TFET circuit architectures in order
to mitigate the pitfalls and take full advantage of the unique TFET properties for
optimal flip-flop design.
This chapter investigates ultra-compact low-voltage flip-flop design using SiTFETs for ULP applications requiring long battery life while providing good
performance. A summary of the area and power efficiency of the existing CMOS
and TFET circuit architectures is presented in Sect. 5.2.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_5
59