4.5 Summary
57
Table 4.1 uDRAM, uSRAM, and uCAM comparison with state-of-the-art CMOS RAM
Proposed
State-of-the-art [58]
uDRAM
uSRAM
uCAM
eDRAM
LV SRAM
Technology (nm)
28
28
28
22
22
Bitcell area (µm 2 )
0.0275
0.07
0.104
0.029
0.092
Refresh req.
No
No
No
Yes
No
Retention time (µs)
Inf
Inf
Inf
100
Inf
Capacitance/node (fF)
2.5
2.5
2.5
14.2
–
Leakage (fA/bit)
< 1
< 1
< 1
> 100
++
Sub-array latency (ns)
< 4
< 1
< 1
3
< 0.5
In a DDR configuration throughput gains of up to 18% are obtained owing
to the removal of refresh, the achieved performance being compatible with DDR
1600 standard timing. The design summary and comparison with state-of-theart is presented in Table 4.1. Far lower leakage for uDRAM, uSRAM, and
uCAM is obtained in comparison to state-of-the-art 22 nm eDRAM and LVSRAM
while maintaining similar performance, bitcell area, and array density despite the
difference in technology node, see Table 4.1. Moreover, the up to 5.6× reduced
value of the uDRAM bitcell capacitance allows a cheaper and more reliable process
integration. The uSRAM bitcell area is 40% smaller than that of the 6T-CMOS
high-density bitcell in 28 nm FDSOI allowing 1.4× more memory in the same
footprint while reducing standby power by a few decades. The availability of uCAM
provides an option to use a built-in CAM with uDRAM or uSRAM embedded on
the same chip, using it as a cache to implement search functions in an area- and
power-efficient way. uCAM is 47% better in area comparison with the high-density
6T-CMOS CAM based on a standard SRAM bitcell [66].