56
4 Ultimate-D/SRAMs/CAMs
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
G[0]
WL[0]
DL[0]
Q[0]
DLB[0]
ML[0]
Q[1]
WL[1]
Q[2]
ML[1]
Q[3]
DL[0]
DLB[0]
G[1]
S
S
S
S
M 1
M 1
M 1
M 1
Fig. 4.15 uCAM 2x2 bitcell array
Contact Active/PolyM1
Contact M1
Contact ActiveM1MIM-CAP
Contact Active and Poly both M1
Contact M2
G
G
WL
WL
DL
DLB
DL
DLB
2x2 array
1-bit
ML
ML
Fig. 4.16 uCAM bitcell layout
area may increase by 10–20%; area estimation with compact-memory design rules
is 0.07 µm 2 and 0.104 µm 2 for uSRAM and uCAM, respectively. Further area
shrinkage for all the proposed designs is possible by using a high-cost process
to implement the access transistor vertically, as in the case of modern DRAMs
[65]. The proposed uDRAM architecture is scalable and can be tuned to meet
performance and area requirements by either adjusting the block sizes or supply
voltages.
4 Ultimate-D/SRAMs/CAMs
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
M 1
C Q
M 2
M 3
G[0]
WL[0]
DL[0]
Q[0]
DLB[0]
ML[0]
Q[1]
WL[1]
Q[2]
ML[1]
Q[3]
DL[0]
DLB[0]
G[1]
S
S
S
S
M 1
M 1
M 1
M 1
Fig. 4.15 uCAM 2x2 bitcell array
Contact Active/PolyM1
Contact M1
Contact ActiveM1MIM-CAP
Contact Active and Poly both M1
Contact M2
G
G
WL
WL
DL
DLB
DL
DLB
2x2 array
1-bit
ML
ML
Fig. 4.16 uCAM bitcell layout
area may increase by 10–20%; area estimation with compact-memory design rules
is 0.07 µm 2 and 0.104 µm 2 for uSRAM and uCAM, respectively. Further area
shrinkage for all the proposed designs is possible by using a high-cost process
to implement the access transistor vertically, as in the case of modern DRAMs
[65]. The proposed uDRAM architecture is scalable and can be tuned to meet
performance and area requirements by either adjusting the block sizes or supply
voltages.