4.2 The Ultimate-DRAM (uDRAM): TFET. . .
47
G=0.5V (medium)
WL=1V (high)
BL=0V (low)
Q=0.5V
G=0.5V (medium)
WL=1V (high)
BL=0V (low)
Q=0V
C s
C s
a.
b.
I
CAPL
I NDR
I
CAPL
I OFF
I NDR >> I CAPL >> I OFF
T A
T A
Fig. 4.1 TFET DRAM bitcell in retention, storing logical “0” and “1” [©2017 IEEE]
A
I CAPL
B
III
II
VGS=1V
1.E-05
1.E-07
1.E-09
1.E-11
0.25V
1.E-13
1.E-15
1.E-17
–1.0
–0.8
–0.6
–0.4
V DS (V)
I D (A/µm)
–0.2
0.0
I
Fig. 4.2 TFET I D = f (reverse-biased V DS ) characteristics and capacitor leakage [©2017 IEEE]
I D = f (−V DS ) device characteristics. The static latch behavior of the bitcell during
retention is achieved with bitline (BL) low at 0 V, wordline (WL) high at 1 V, and
the virtual ground node G connected through capacitor C s to the storage node Q, at
0.5 V. With this setup the bitcell is biased in point A when storing a “0” with access
transistor T A operating in region I with low V DS (0 V) and high V GS (1 V), see
Fig. 4.2. Two currents pull node Q in opposite directions, I CAP L trying to charge
up node Q while transistor T A starting to discharge node Q due to I NDR (region
I) as soon as the voltage on Q > 0 V. Since I NDR >> I CAP L , 0 V representing
logic “0” is maintained indefinitely in a static manner on Q. In the case the bitcell
is storing a “1” the voltage across C s is 0 V and T A is in reverse bias in point B
with V DS = −0.5 V, see Fig. 4.2. Node Q will attempt to discharge through T A due
to I OF F while at the same time I CAP L keeps recharging node Q as soon as it goes
below the node G voltage (i.e., 0.5 V). Since, I CAP L >> I OF F (region II), the value
of 0.5 V on node Q is maintained.
As the charge on the cell capacitor is maintained statically during retention
the uDRAM presents the following advantages: (1) Significant improvement in
terms of throughput and energy consumption due to refresh removal; (2) Unlike
conventional CMOS DRAMs where capacitor scaling is limited by leakage and the
higher retention time requirement, in the proposed design the minimum capacitor
47
G=0.5V (medium)
WL=1V (high)
BL=0V (low)
Q=0.5V
G=0.5V (medium)
WL=1V (high)
BL=0V (low)
Q=0V
C s
C s
a.
b.
I
CAPL
I NDR
I
CAPL
I OFF
I NDR >> I CAPL >> I OFF
T A
T A
Fig. 4.1 TFET DRAM bitcell in retention, storing logical “0” and “1” [©2017 IEEE]
A
I CAPL
B
III
II
VGS=1V
1.E-05
1.E-07
1.E-09
1.E-11
0.25V
1.E-13
1.E-15
1.E-17
–1.0
–0.8
–0.6
–0.4
V DS (V)
I D (A/µm)
–0.2
0.0
I
Fig. 4.2 TFET I D = f (reverse-biased V DS ) characteristics and capacitor leakage [©2017 IEEE]
I D = f (−V DS ) device characteristics. The static latch behavior of the bitcell during
retention is achieved with bitline (BL) low at 0 V, wordline (WL) high at 1 V, and
the virtual ground node G connected through capacitor C s to the storage node Q, at
0.5 V. With this setup the bitcell is biased in point A when storing a “0” with access
transistor T A operating in region I with low V DS (0 V) and high V GS (1 V), see
Fig. 4.2. Two currents pull node Q in opposite directions, I CAP L trying to charge
up node Q while transistor T A starting to discharge node Q due to I NDR (region
I) as soon as the voltage on Q > 0 V. Since I NDR >> I CAP L , 0 V representing
logic “0” is maintained indefinitely in a static manner on Q. In the case the bitcell
is storing a “1” the voltage across C s is 0 V and T A is in reverse bias in point B
with V DS = −0.5 V, see Fig. 4.2. Node Q will attempt to discharge through T A due
to I OF F while at the same time I CAP L keeps recharging node Q as soon as it goes
below the node G voltage (i.e., 0.5 V). Since, I CAP L >> I OF F (region II), the value
of 0.5 V on node Q is maintained.
As the charge on the cell capacitor is maintained statically during retention
the uDRAM presents the following advantages: (1) Significant improvement in
terms of throughput and energy consumption due to refresh removal; (2) Unlike
conventional CMOS DRAMs where capacitor scaling is limited by leakage and the
higher retention time requirement, in the proposed design the minimum capacitor