46
4 Ultimate-D/SRAMs/CAMs
is implemented in eDRAM with planar process achieving 22.1M bits/mm 2 array
density, providing only 100 µs retention time while using NWL to reduce transistor
leakage. The achieved refresh power is 1.5 W/Gbit, which is 30% of the eDRAMs
peak active power consumption. Another critical issue specifically for eDRAMs
is that the leakage increases significantly at high temperatures, which is often the
case for memory placed in close proximity to compute-intensive blocks such as
CPUs/GPUs. For example in JEDEC DDR specifications [61], the refresh time
interval (tRFEI) is reduced by 50% for operation above 85 ◦ C due to increased
leakage in bitcells. The impact of refresh on throughput can be up to 18% due to
read/write traffic interruption caused by refresh commands and higher leakage at
elevated temperatures.
In order to address the aforementioned DRAM design challenges, other than
CMOS technologies have been explored. The Tunnel Field Effect Transistor (TFET)
was proposed as a possible solution to reduce leakage while having the same
scalability as MOSFETs. The conventional 1T1C DRAM architecture with TFET
cannot work the same way as in CMOS because of the unidirectional current
conduction. Therefore, there is a need to optimize the DRAM cell specifically for
TFETs in order to utilize its advantageous properties over CMOS.
In [62] a capacitor-less TFET DRAM is shown using the potential well in a
FDSOI-CMOS process. Retention times from hundreds of µs to ms are reported.
However, predicting the stability is not possible with the present state of TFET
device process variations and therefore, it is difficult to estimate the reliability of
these circuits once fabricated.
The following sections present a refresh-free and scalable ultimate-DRAM
(uDRAM) and its extension to SRAMs and CAMs for embedded applications.
These memories are implemented with Si-TFETs and MIM capacitors using a 28 nm
FDSOI-CMOS process, which allows co-fabrication of CMOS and TFETs.
4.2 The Ultimate-DRAM (uDRAM): TFET
Negative-Differential-Resistance-Based 1T1C
Refresh-Free DRAM
The uDRAM [63] relies on the Negative Differential Resistance (NDR) of the TFET
observed in reverse bias as introduced in Chap. 2. The uDRAM bitcell utilizes the I D
as a function of reverse-biased V DS characteristics of TFETs differing in operation
from a CMOS DRAM cell; the 1T1C ultimate-DRAM cell consists of a TFET
and a capacitor behaving as a static latch during retention. Figure 4.1a, b show the
bitcell with the current and voltage setup during retention for storing a logical “0”
and “1,” respectively. In order to implement static-latch behavior during retention,
the cell is designed to have I OF F (device off-state current) << I CAP L (leakage
current in capacitor) << I NDR (device current due to NDR property of TFET). The
relation between currents and capacitor leakage is shown in Fig. 4.2 on the TFET
4 Ultimate-D/SRAMs/CAMs
is implemented in eDRAM with planar process achieving 22.1M bits/mm 2 array
density, providing only 100 µs retention time while using NWL to reduce transistor
leakage. The achieved refresh power is 1.5 W/Gbit, which is 30% of the eDRAMs
peak active power consumption. Another critical issue specifically for eDRAMs
is that the leakage increases significantly at high temperatures, which is often the
case for memory placed in close proximity to compute-intensive blocks such as
CPUs/GPUs. For example in JEDEC DDR specifications [61], the refresh time
interval (tRFEI) is reduced by 50% for operation above 85 ◦ C due to increased
leakage in bitcells. The impact of refresh on throughput can be up to 18% due to
read/write traffic interruption caused by refresh commands and higher leakage at
elevated temperatures.
In order to address the aforementioned DRAM design challenges, other than
CMOS technologies have been explored. The Tunnel Field Effect Transistor (TFET)
was proposed as a possible solution to reduce leakage while having the same
scalability as MOSFETs. The conventional 1T1C DRAM architecture with TFET
cannot work the same way as in CMOS because of the unidirectional current
conduction. Therefore, there is a need to optimize the DRAM cell specifically for
TFETs in order to utilize its advantageous properties over CMOS.
In [62] a capacitor-less TFET DRAM is shown using the potential well in a
FDSOI-CMOS process. Retention times from hundreds of µs to ms are reported.
However, predicting the stability is not possible with the present state of TFET
device process variations and therefore, it is difficult to estimate the reliability of
these circuits once fabricated.
The following sections present a refresh-free and scalable ultimate-DRAM
(uDRAM) and its extension to SRAMs and CAMs for embedded applications.
These memories are implemented with Si-TFETs and MIM capacitors using a 28 nm
FDSOI-CMOS process, which allows co-fabrication of CMOS and TFETs.
4.2 The Ultimate-DRAM (uDRAM): TFET
Negative-Differential-Resistance-Based 1T1C
Refresh-Free DRAM
The uDRAM [63] relies on the Negative Differential Resistance (NDR) of the TFET
observed in reverse bias as introduced in Chap. 2. The uDRAM bitcell utilizes the I D
as a function of reverse-biased V DS characteristics of TFETs differing in operation
from a CMOS DRAM cell; the 1T1C ultimate-DRAM cell consists of a TFET
and a capacitor behaving as a static latch during retention. Figure 4.1a, b show the
bitcell with the current and voltage setup during retention for storing a logical “0”
and “1,” respectively. In order to implement static-latch behavior during retention,
the cell is designed to have I OF F (device off-state current) << I CAP L (leakage
current in capacitor) << I NDR (device current due to NDR property of TFET). The
relation between currents and capacitor leakage is shown in Fig. 4.2 on the TFET