Chapter 4
Ultimate-D/SRAMs/CAMs
4.1 Introduction
On-chip storage demand is continuously increasing due to the higher complexity
of SoCs. It is important to scale memory aggressively in order to increase on-chip
memory capacity in a cost-efficient manner. In the past, technology scaling was key
to augment the on-chip SRAM. However, at new technology nodes challenges such
as increasing leakage and variations are limiting scaling SRAM capacity further.
Therefore, researchers are exploring alternative options, such as Embedded-DRAMs
(eDRAMs) and Embedded-Flash (eFlash), to improve memory density.
The use of eFlash is limited due to its reduced write endurance and higher operating voltage than that of standard CMOS digital logic. eDRAMs are a promising
alternative, however, they have their own limitations such as refresh, and a costlier
process due to the vertical storage capacitors. There have been several reports in
literature focusing on eDRAMs to improve the array density and to reduce cost
[55–58]. An intermediate solution for deploying eDRAM is to reduce the density
in eDRAMs compared to standard DRAMs and thus enabling implementation in
a standard CMOS process for digital logic [58–60]. However, technology raises
challenges in scaling the standard 1T1C DRAM structure because of difficulties in
scaling the capacitor as it needs a high value to limit the refresh rate and reduce the
throughput penalty. The ITRS roadmap [3] shows a 20% reduction of the required
DRAM cell capacitance to store 1 bit from year 2009 to 2016 whereas in the same
time period transistor technology scaled by 57% from 52 nm to 22 nm. Various
techniques such as negative wordline (NWL) and high-oxide-thickness capacitors
are used in DRAMs to reduce leakage and thus to increase retention time. eDRAM
capacitors in [55] are using an effective oxide thickness (EOT) of 0.7 nm to get
8 fF/bit capacitance with 0.1 fA/bit leakage. However, the EOT of 0.3 nm, suggested
by ITRS for DRAM capacitors [3], would result in significantly increased capacitor
leakage. In eDRAMs capacitor size is reduced at the cost of retention time in order
to optimize cost of process and silicon footprint. In [58], a 14.2 fF/bit capacitance
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_4
45
Ultimate-D/SRAMs/CAMs
4.1 Introduction
On-chip storage demand is continuously increasing due to the higher complexity
of SoCs. It is important to scale memory aggressively in order to increase on-chip
memory capacity in a cost-efficient manner. In the past, technology scaling was key
to augment the on-chip SRAM. However, at new technology nodes challenges such
as increasing leakage and variations are limiting scaling SRAM capacity further.
Therefore, researchers are exploring alternative options, such as Embedded-DRAMs
(eDRAMs) and Embedded-Flash (eFlash), to improve memory density.
The use of eFlash is limited due to its reduced write endurance and higher operating voltage than that of standard CMOS digital logic. eDRAMs are a promising
alternative, however, they have their own limitations such as refresh, and a costlier
process due to the vertical storage capacitors. There have been several reports in
literature focusing on eDRAMs to improve the array density and to reduce cost
[55–58]. An intermediate solution for deploying eDRAM is to reduce the density
in eDRAMs compared to standard DRAMs and thus enabling implementation in
a standard CMOS process for digital logic [58–60]. However, technology raises
challenges in scaling the standard 1T1C DRAM structure because of difficulties in
scaling the capacitor as it needs a high value to limit the refresh rate and reduce the
throughput penalty. The ITRS roadmap [3] shows a 20% reduction of the required
DRAM cell capacitance to store 1 bit from year 2009 to 2016 whereas in the same
time period transistor technology scaled by 57% from 52 nm to 22 nm. Various
techniques such as negative wordline (NWL) and high-oxide-thickness capacitors
are used in DRAMs to reduce leakage and thus to increase retention time. eDRAM
capacitors in [55] are using an effective oxide thickness (EOT) of 0.7 nm to get
8 fF/bit capacitance with 0.1 fA/bit leakage. However, the EOT of 0.3 nm, suggested
by ITRS for DRAM capacitors [3], would result in significantly increased capacitor
leakage. In eDRAMs capacitor size is reduced at the cost of retention time in order
to optimize cost of process and silicon footprint. In [58], a 14.2 fF/bit capacitance
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_4
45