3.5 Summary
43
0
1
10
100
0,3
0,4
0,5
0,6
RdTime
Rd@NWL
Rd@NWL-150mV
WrTime
Wr@WA
]
s
n
[
y
a
l
e
D
Cell Supply Voltage [V]
Read/Write with assist techniques
0.3
0.4
0.5
0.6
4.8x
29x
Fig. 3.27 Read/Write performance (WLPcrit) vs. cell supply voltage, including improvements
with read/write-assist techniques [©2016 IEEE]
3.5 Summary
This chapter presents TFET/CMOS hybrid SRAM solutions for both typicalvoltage/high-performance and ultra-compact/low-voltage/low performance applications. An 8T-TFET bitcell-based Dual-Port SRAM is proposed, which can work
from 0.6 V to 1 V providing ultra-low standby power while maintaining good
performance and stability. The achieved leakage is less than 5 fA/bit by controlling
voltage bias to limit high reverse-bias TFET parasitic current. The WLPcrit of
377 ps is achieved for a supply voltage of 1 V and write speed improvements up
to 79.2% are obtained with NBL write assist of 150 mV. The presented design uses
four voltages, which can be optimized to three voltages either by limiting the highest
voltage of operation to 0.9 V or, at the cost of increased leakage at 1 V operation.
For low-voltage applications, a novel integrated 3T-TFET bitcell-based TFET/CMOS hybrid SRAM architecture was introduced in this chapter; TFETs are used
for the memory array due to ultra-low leakage and CMOS for the periphery. The
proposed 3T-TFET bitcell uses an NDR-based 2T-TFET latch for data storage and
1 TFET for the read port; it implements a new write mechanism using supply
lines. The proposed design supports voltage scaling and works from 0.6 V to 0.3 V
bitcell supply voltages; memory cells have an ultra-low leakage current less than
0.35 fA/bit. Read/write speed improvement of up to 70% and 90% can be achieved
using assist techniques for 0.4 V and 0.3 V cell supply, respectively.
43
0
1
10
100
0,3
0,4
0,5
0,6
RdTime
Rd@NWL
Rd@NWL-150mV
WrTime
Wr@WA
]
s
n
[
y
a
l
e
D
Cell Supply Voltage [V]
Read/Write with assist techniques
0.3
0.4
0.5
0.6
4.8x
29x
Fig. 3.27 Read/Write performance (WLPcrit) vs. cell supply voltage, including improvements
with read/write-assist techniques [©2016 IEEE]
3.5 Summary
This chapter presents TFET/CMOS hybrid SRAM solutions for both typicalvoltage/high-performance and ultra-compact/low-voltage/low performance applications. An 8T-TFET bitcell-based Dual-Port SRAM is proposed, which can work
from 0.6 V to 1 V providing ultra-low standby power while maintaining good
performance and stability. The achieved leakage is less than 5 fA/bit by controlling
voltage bias to limit high reverse-bias TFET parasitic current. The WLPcrit of
377 ps is achieved for a supply voltage of 1 V and write speed improvements up
to 79.2% are obtained with NBL write assist of 150 mV. The presented design uses
four voltages, which can be optimized to three voltages either by limiting the highest
voltage of operation to 0.9 V or, at the cost of increased leakage at 1 V operation.
For low-voltage applications, a novel integrated 3T-TFET bitcell-based TFET/CMOS hybrid SRAM architecture was introduced in this chapter; TFETs are used
for the memory array due to ultra-low leakage and CMOS for the periphery. The
proposed 3T-TFET bitcell uses an NDR-based 2T-TFET latch for data storage and
1 TFET for the read port; it implements a new write mechanism using supply
lines. The proposed design supports voltage scaling and works from 0.6 V to 0.3 V
bitcell supply voltages; memory cells have an ultra-low leakage current less than
0.35 fA/bit. Read/write speed improvement of up to 70% and 90% can be achieved
using assist techniques for 0.4 V and 0.3 V cell supply, respectively.