42
3 SRAMs
to 100 mV for 6T-SRAM with differential read. E W RI T E is the energy consumed
during write. I LEAK in active mode is the total leakage in the bitcell array and
periphery with dynamic power gating (only 25% of the drivers are switched ON
depending on the accessed address). I LEAK in standby mode is computed with the
periphery OFF and the bitcell power ON to retain the data.
The leakage power per driver of a row of the 3T TFET cells is 52% and 85% less
in comparison to that of the 6T-CMOS and 8T-TFET SRAMs, respectively. Three
drivers per row are required in this design resulting in 42% increased leakage per
row in comparison to the 6T-CMOS high-density (HD) SRAM; however, the driver
leakage per row is still 77% less in comparison to the 8T-TFET SRAM, even with
two drivers per row, which have high capacitance and longer wordlines due to a
larger bitcell size. The bitcell array leakage is 10 4 × and 77× lower compared to
that of the 6T-CMOS (HD) [18] and ultra-low leakage 6T-65 nm CMOS SRAM [8]
cells, respectively. Bitcell leakage is 14× lower in comparison to 8T-TFET SRAM
cells [32]. During standby the total leakage is coming from the cell array, thus TFET
memory leakage is much lower than that of CMOS memories. Overall memory
leakage during active mode including bitcells and drivers for the proposed design is
52% lower than for 6T-CMOS and 77% lower than for 8T-TFET SRAMs.
Dynamic power consumption of the 3T-TFET cell design is 70% less in
comparison to the 6T-CMOS SRAM and up to 90% less in comparison to the 8TTFET SRAM due to the low capacitance on VD, VS, and RWL lines.
3.4.5 Read and Write Performance
Read and write minimum wordline pulse width (WLPcrit) is plotted as a function
of supply voltage in Fig. 3.27. For the full range of operation cell leakage is
<0.35 fA/bit because devices M0 and M1 are in reverse bias during retention. As
shown in Fig. 3.27, the read/write speed can be increased by using assist techniques
for low-voltage operation. Since the cell data storage node is isolated from RBL and
the bias voltages of M0 and M1, negative wordline (NWL) can be used to increase
read speed without impacting the cell stability. Similarly, for write the speed can
be increased without impacting cell stability by boosting bias voltages BiasM0 and
BiasM1. Read performance is improved by 29×, by using NWL of −100 mV and
−150 mV for supply voltages of 0.4 V and 0.3 V, respectively, on read wordline
RWL. A boost of 100 mV on the gate-bias voltage of M0 and M1 results in a 4.8×
improvement at 0.3 V cell supply for write operation.
The overall performance is estimated including periphery delays in the row
decoder, drivers, and sensing. The proposed design supports overall read speed from
1.92 GHz to 3.82 MHz and write speed from 429 MHz to 17.3 MHz for 0.6 V to
0.3 V cell supply voltages, respectively, with corresponding BiasM0 and BiasM1
values from 1.2 V to 0.6 V. Therefore, this implementation requires a total of five
voltages, which can be implemented either using five supplies or three supplies with
two voltage dividers inside the memory.
3 SRAMs
to 100 mV for 6T-SRAM with differential read. E W RI T E is the energy consumed
during write. I LEAK in active mode is the total leakage in the bitcell array and
periphery with dynamic power gating (only 25% of the drivers are switched ON
depending on the accessed address). I LEAK in standby mode is computed with the
periphery OFF and the bitcell power ON to retain the data.
The leakage power per driver of a row of the 3T TFET cells is 52% and 85% less
in comparison to that of the 6T-CMOS and 8T-TFET SRAMs, respectively. Three
drivers per row are required in this design resulting in 42% increased leakage per
row in comparison to the 6T-CMOS high-density (HD) SRAM; however, the driver
leakage per row is still 77% less in comparison to the 8T-TFET SRAM, even with
two drivers per row, which have high capacitance and longer wordlines due to a
larger bitcell size. The bitcell array leakage is 10 4 × and 77× lower compared to
that of the 6T-CMOS (HD) [18] and ultra-low leakage 6T-65 nm CMOS SRAM [8]
cells, respectively. Bitcell leakage is 14× lower in comparison to 8T-TFET SRAM
cells [32]. During standby the total leakage is coming from the cell array, thus TFET
memory leakage is much lower than that of CMOS memories. Overall memory
leakage during active mode including bitcells and drivers for the proposed design is
52% lower than for 6T-CMOS and 77% lower than for 8T-TFET SRAMs.
Dynamic power consumption of the 3T-TFET cell design is 70% less in
comparison to the 6T-CMOS SRAM and up to 90% less in comparison to the 8TTFET SRAM due to the low capacitance on VD, VS, and RWL lines.
3.4.5 Read and Write Performance
Read and write minimum wordline pulse width (WLPcrit) is plotted as a function
of supply voltage in Fig. 3.27. For the full range of operation cell leakage is
<0.35 fA/bit because devices M0 and M1 are in reverse bias during retention. As
shown in Fig. 3.27, the read/write speed can be increased by using assist techniques
for low-voltage operation. Since the cell data storage node is isolated from RBL and
the bias voltages of M0 and M1, negative wordline (NWL) can be used to increase
read speed without impacting the cell stability. Similarly, for write the speed can
be increased without impacting cell stability by boosting bias voltages BiasM0 and
BiasM1. Read performance is improved by 29×, by using NWL of −100 mV and
−150 mV for supply voltages of 0.4 V and 0.3 V, respectively, on read wordline
RWL. A boost of 100 mV on the gate-bias voltage of M0 and M1 results in a 4.8×
improvement at 0.3 V cell supply for write operation.
The overall performance is estimated including periphery delays in the row
decoder, drivers, and sensing. The proposed design supports overall read speed from
1.92 GHz to 3.82 MHz and write speed from 429 MHz to 17.3 MHz for 0.6 V to
0.3 V cell supply voltages, respectively, with corresponding BiasM0 and BiasM1
values from 1.2 V to 0.6 V. Therefore, this implementation requires a total of five
voltages, which can be implemented either using five supplies or three supplies with
two voltage dividers inside the memory.