3.4 3T-TFET Bitcell-Based TFET-CMOS Hybrid Memory
41
Table 3.1
Comparison - power and area [©2016 IEEE]
Cell
VDD (V)
WL
Pulse
Read (ns)
WL
Pulse
Write (ns)
E
READ
(fJ/acc.)
E
WRITE
(fJ/acc.)
E
AVG
(fJ/acc.)
I
LEAK
Active
(pA/bit)
I
LEAK
STBY
(fA/bit)
Area-Bitcell
(µm 2
)
8T-TFET
1
0.26
1.10
28.5
61.0
44.8
25.5
5.00
0.336
6T-CMOS
0.75
0.27
0.16
9.10
12.9
11.0
11.8
7.8 ∗
10 3
0.120
3T-TFET [proposed] 0.6
0.21
0.93
1.81
4.99
3.40
5.72
0.35
0.1266
6T-CMOS [8]
1.2
7 ns (access time) a
N.A.
N.A.
25
µW/MHz a
N.A.
27.0
2.04
a
Measurement values reported for full memory [8]