3.4 3T-TFET Bitcell-Based TFET-CMOS Hybrid Memory
39
I/O Logic
TFET
SRAM
Array
64x32
TFET
SRAM
Array
64x32
RBL SA
BL Driver
Write Logic
MemCell[0]
WL Drivers
I/O Logic
TFET
SRAM
Array
64x32
TFET
SRAM
Array
64x32
Controller
MemCell[63]
MemCell[63]
MemCell[0]
WL Drivers
Fig. 3.25 Proposed TFET/CMOS hybrid memory architecture [©2016 IEEE]
The proposed memory architecture is shown in Fig. 3.25. In order to optimize
the cell array leakage current the bitcell array is designed only with TFETs while
the periphery uses CMOS to optimize the area for the same speed of operation
due to its higher drive strength when compared to that of TFETs. We have used
the single-ended skewed inverter-based sense amplifier for reading, described in
Chap. 7, Sect. 7.4.1, to limit the bitline discharge, to reduce power consumption,
and to allow for a larger column size.
3.4.3 Memory Layout
The layout for the dual-cell block and the 64 × 32 cell array is shown in Fig. 3.26.
The cell size is 0.1266 µm 2 /bit using 28 nm FDSOI process logic design rules;
this area is similar to that of an industrial high-density 6T-CMOS cell, which is
implemented using compact design rules instead of logic design rules. In this layout
the TFET M2 (200 nm) on the read port is twice the size of M0 and M1 (100 nm).
This improves the read speed of the design. In order to achieve an optimized
rectangular layout of the memory cell, two bitcells are layed out together to have
six transistors within a dual-bitcell layout structure, see Fig. 3.26. Cell boundaries
are represented by dotted lines to show each cell separately. Due to the reduced cell
width the wiring capacitances on the various horizontal lines in the cell array are
reduced. The capacitance values of metal lines extracted from the layout represent
only 50% of those of an identical-size memory array designed using the compact 6TSRAM cell. This reduction combined with a low C GS capacitance of TFET devices
cuts the total capacitance on VD, VS, and RWL lines to less than half resulting
39
I/O Logic
TFET
SRAM
Array
64x32
TFET
SRAM
Array
64x32
RBL SA
BL Driver
Write Logic
MemCell[0]
WL Drivers
I/O Logic
TFET
SRAM
Array
64x32
TFET
SRAM
Array
64x32
Controller
MemCell[63]
MemCell[63]
MemCell[0]
WL Drivers
Fig. 3.25 Proposed TFET/CMOS hybrid memory architecture [©2016 IEEE]
The proposed memory architecture is shown in Fig. 3.25. In order to optimize
the cell array leakage current the bitcell array is designed only with TFETs while
the periphery uses CMOS to optimize the area for the same speed of operation
due to its higher drive strength when compared to that of TFETs. We have used
the single-ended skewed inverter-based sense amplifier for reading, described in
Chap. 7, Sect. 7.4.1, to limit the bitline discharge, to reduce power consumption,
and to allow for a larger column size.
3.4.3 Memory Layout
The layout for the dual-cell block and the 64 × 32 cell array is shown in Fig. 3.26.
The cell size is 0.1266 µm 2 /bit using 28 nm FDSOI process logic design rules;
this area is similar to that of an industrial high-density 6T-CMOS cell, which is
implemented using compact design rules instead of logic design rules. In this layout
the TFET M2 (200 nm) on the read port is twice the size of M0 and M1 (100 nm).
This improves the read speed of the design. In order to achieve an optimized
rectangular layout of the memory cell, two bitcells are layed out together to have
six transistors within a dual-bitcell layout structure, see Fig. 3.26. Cell boundaries
are represented by dotted lines to show each cell separately. Due to the reduced cell
width the wiring capacitances on the various horizontal lines in the cell array are
reduced. The capacitance values of metal lines extracted from the layout represent
only 50% of those of an identical-size memory array designed using the compact 6TSRAM cell. This reduction combined with a low C GS capacitance of TFET devices
cuts the total capacitance on VD, VS, and RWL lines to less than half resulting