3.4 3T-TFET Bitcell-Based TFET-CMOS Hybrid Memory
35
BiasM0
VD
VS
BiasM1
RWL
RBL
BiasM1
VD
VS
BiasM0
RWL
RBL
Qint
Qint
a.
b.
M0
M1
M1
M0
M2
M2
Fig. 3.19 Proposed 3T-SRAM cell architectures [©2016 IEEE]
Fig. 3.20 I D for DC sweep
on node Qint at 0.6 V cell
supply [©2016 IEEE]
0
20
40
60
80
100
120
140
0.00 0.10 0.20 0.30 0.40 0.50
I D (M0)
I D (M1)
Current [pA]
Node Qint Voltage [V]
100 mV
V margin >= 0
The read operation is performed using the RBL and RWL lines with RBL
precharged and RWL active low. The write operation is performed using a combination of voltages on VD, VS, and BiasM0/BiasM1, which enables storing a “0”
or a “1” in the cell on node Qint. The various operating modes are described in the
following subsections.
Two versions of the proposed cell are shown in Fig. 3.19a, b. The circuit shown
in Fig. 3.19a provides high write speed and low capacitance on the supply nodes
VD and VS because of a low C GS in TFETs and constant V GS during write for M0
and M1. In the circuit shown in Fig. 3.19b, having the two TFET sources connected
together at Qint, V GS for M0 and M1 is continuously changing with V Qint during the
write operation resulting in a performance penalty. However, this circuit is better in
terms of stability due to higher hump current and higher V GS for M0 and M1 during
retention mode.
3.4.1.1 Retention Mode and Stability
The information in the cell is stored on node Qint during write by forward biasing
one of the transistors and turning the other one off. Figure 3.20 shows I D of M0
and M1 as a function of V Qint ; BiasM0/BiasM1 for the circuits shown in Fig. 3.19
in retention have values such that the TFETs are turned on in reverse-V DS mode.
The state of the cell “0” and “1” set during a write is represented by one of the
two humps. As both TFETs operate in the NDR region, M0 preserves the “0” (V V S )
35
BiasM0
VD
VS
BiasM1
RWL
RBL
BiasM1
VD
VS
BiasM0
RWL
RBL
Qint
Qint
a.
b.
M0
M1
M1
M0
M2
M2
Fig. 3.19 Proposed 3T-SRAM cell architectures [©2016 IEEE]
Fig. 3.20 I D for DC sweep
on node Qint at 0.6 V cell
supply [©2016 IEEE]
0
20
40
60
80
100
120
140
0.00 0.10 0.20 0.30 0.40 0.50
I D (M0)
I D (M1)
Current [pA]
Node Qint Voltage [V]
100 mV
V margin >= 0
The read operation is performed using the RBL and RWL lines with RBL
precharged and RWL active low. The write operation is performed using a combination of voltages on VD, VS, and BiasM0/BiasM1, which enables storing a “0”
or a “1” in the cell on node Qint. The various operating modes are described in the
following subsections.
Two versions of the proposed cell are shown in Fig. 3.19a, b. The circuit shown
in Fig. 3.19a provides high write speed and low capacitance on the supply nodes
VD and VS because of a low C GS in TFETs and constant V GS during write for M0
and M1. In the circuit shown in Fig. 3.19b, having the two TFET sources connected
together at Qint, V GS for M0 and M1 is continuously changing with V Qint during the
write operation resulting in a performance penalty. However, this circuit is better in
terms of stability due to higher hump current and higher V GS for M0 and M1 during
retention mode.
3.4.1.1 Retention Mode and Stability
The information in the cell is stored on node Qint during write by forward biasing
one of the transistors and turning the other one off. Figure 3.20 shows I D of M0
and M1 as a function of V Qint ; BiasM0/BiasM1 for the circuits shown in Fig. 3.19
in retention have values such that the TFETs are turned on in reverse-V DS mode.
The state of the cell “0” and “1” set during a write is represented by one of the
two humps. As both TFETs operate in the NDR region, M0 preserves the “0” (V V S )