34
3 SRAMs
3.4 3T-TFET Bitcell-Based TFET-CMOS Hybrid Memory
In Sect. 3.3, a TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad
memory was presented with ultra-low leakage current (<5 fA/bit) and 29% increased
area in comparison to an industrial 6T-CMOS SRAM. However, dynamic power
consumption for these memories is more than that of a 6T-CMOS because of
increased load on high-capacitance nodes, such as wordlines. An alternative is
offered in [37, 38], where TFET latches and memory cells using the NDR property
of TFETs in reverse bias are presented. The NDR property of TFETs [14] is very
promising for designing a compact latch; however, the architecture proposed in [38]
suffers from stability and performance issues. In order to maintain data during read,
the read current should be less than the hump current (in pA range) provided by
NDR. This constraint leads to an extremely slow read with the risk of data corruption
while executing the operation; additionally, the TFET transmission gate for data
access limits the maximum operating voltage.
This section provides insight into an ultra-compact SRAM design using SiTFETs [14] compatible with CMOS for ultra-low power applications with ultralow leakage for long battery life time and good performance. We analyzed the
architecture-level issues in TFET SRAM design and demonstrate a novel 3TTFET SRAM cell designed using the NDR property of TFETs in reverse bias.
The proposed design supports aggressive voltage scaling without impacting data
stability of the cell and allows the application of performance-boosting techniques
without impacting cell leakage. The new cell maintains reasonable stability in all
operation modes without using any assist technique. Based on this 3T-TFET bitcell
a TFET/CMOS hybrid memory architecture is proposed using CMOS peripheral
circuits.
3.4.1 Proposed 3T-TFET SRAM Cell
The key concept of the 3T-TFET SRAM bitcell [54] based on a static latch using
NDR with two TFET devices, one NTFET (M1) and one PTFET (M0) is shown in
Fig. 3.19. The two supplies VD and VS assume different values depending on the
mode of operation of the cell.
During retention the voltages on VD and VS insure that devices M0 and M1
are reverse biased with 0 < V V D − V V S ≤ 0.6 V and BiasM0/BiasM1 are chosen
such that both devices get sufficient gate drive for large enough hump currents, see
Chap. 2, Fig. 2.5. The I D vs. V Qint characteristics for the two TFET devices M0
and M1 connected in series with reverse biased V DS applied are shown in Fig. 3.20.
This transistor configuration biased as above results in a latch behavior with the
condition that the total cell supply be limited to the critical value where the TFET
current becomes independent of gate voltage; for our devices this point is at 0.6 V.
3 SRAMs
3.4 3T-TFET Bitcell-Based TFET-CMOS Hybrid Memory
In Sect. 3.3, a TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad
memory was presented with ultra-low leakage current (<5 fA/bit) and 29% increased
area in comparison to an industrial 6T-CMOS SRAM. However, dynamic power
consumption for these memories is more than that of a 6T-CMOS because of
increased load on high-capacitance nodes, such as wordlines. An alternative is
offered in [37, 38], where TFET latches and memory cells using the NDR property
of TFETs in reverse bias are presented. The NDR property of TFETs [14] is very
promising for designing a compact latch; however, the architecture proposed in [38]
suffers from stability and performance issues. In order to maintain data during read,
the read current should be less than the hump current (in pA range) provided by
NDR. This constraint leads to an extremely slow read with the risk of data corruption
while executing the operation; additionally, the TFET transmission gate for data
access limits the maximum operating voltage.
This section provides insight into an ultra-compact SRAM design using SiTFETs [14] compatible with CMOS for ultra-low power applications with ultralow leakage for long battery life time and good performance. We analyzed the
architecture-level issues in TFET SRAM design and demonstrate a novel 3TTFET SRAM cell designed using the NDR property of TFETs in reverse bias.
The proposed design supports aggressive voltage scaling without impacting data
stability of the cell and allows the application of performance-boosting techniques
without impacting cell leakage. The new cell maintains reasonable stability in all
operation modes without using any assist technique. Based on this 3T-TFET bitcell
a TFET/CMOS hybrid memory architecture is proposed using CMOS peripheral
circuits.
3.4.1 Proposed 3T-TFET SRAM Cell
The key concept of the 3T-TFET SRAM bitcell [54] based on a static latch using
NDR with two TFET devices, one NTFET (M1) and one PTFET (M0) is shown in
Fig. 3.19. The two supplies VD and VS assume different values depending on the
mode of operation of the cell.
During retention the voltages on VD and VS insure that devices M0 and M1
are reverse biased with 0 < V V D − V V S ≤ 0.6 V and BiasM0/BiasM1 are chosen
such that both devices get sufficient gate drive for large enough hump currents, see
Chap. 2, Fig. 2.5. The I D vs. V Qint characteristics for the two TFET devices M0
and M1 connected in series with reverse biased V DS applied are shown in Fig. 3.20.
This transistor configuration biased as above results in a latch behavior with the
condition that the total cell supply be limited to the critical value where the TFET
current becomes independent of gate voltage; for our devices this point is at 0.6 V.