32
3 SRAMs
Fig. 3.16 Minimum
wordline pulse width
requirement vs. memory
supply [©2015 IEEE]
0.0
2.0
4.0
6.0
8.0
10.0
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
WLPcrit-Write
WLPcrit-Read
Time (ns)
Supply Voltage (V)
Write Assist(WA) Disabled
WA Enabled
VDD rise of internal node voltage is due to the non-saturating I D (V DS ) of TFETs.
The negative bitline (NBL) seems to be best suited for TFET SRAM cells in order
to reduce VDD and maintain speed. TFETs used for implementation have V OF F
voltage of 150 mV as described in Chap. 2. Because of very-low leakage current
in TFETs for V GS < V OF F , the power consumption penalty and stability issue of
WD cells is negligible with negative bitline write assist down to −150 mV. With
150 mV negative bitline, 79.2% to 54.7% performance improvement was achieved
for a supply voltage range from 0.6 V to 0.9 V, respectively. Without write assist
WLPcrit for write is more than 40 ns for a supply below 0.6 V while with write
assist enabled WLPcrit is less than 17 ns at 0.5 V supply voltage. Above 0.9 V supply
voltage WLPcrit is less than 1 ns with write assist disabled (see Fig. 3.15).
3.3.6 8T-TFET SRAM Stability and Performance
The performance and stability of the 8T dual-port TFET SRAM was analyzed for
a range of supply voltages for applying DVFS. Figure 3.16 shows the WLPcrit for
write and read operation of the designed 32 Kb memory; in order to keep the delay
at reasonable values Write-Assist (WA) techniques are applied if VDD is lowered
below 0.9 V. The achieved WLPcrit for read and write at 1 V supply is 681 ps and
377 ps, respectively.
Figure 3.17 shows the RSNM and WSNM for different supply voltages. The
achieved noise-margin values at 1 V supply are 114 mV for RSNM and 185 mV
for WSNM. An improvement of approximately 5× and 8× in RSNM and WSNM,
respectively, is observed in comparison to computed margins for a standard 6T
TFET SRAM cell with outward access transistors in the balanced case [31]. The
achieved RSNM and WSNM are sufficient for supply voltages of 1 V and above.
At lower voltages noise margins can be increased by applying assist techniques for
read and write resulting in higher RSNM and WSNM, which enable the use of long
wordlines with bit interleaving without any HS problem. In a TFET the leakage
3 SRAMs
Fig. 3.16 Minimum
wordline pulse width
requirement vs. memory
supply [©2015 IEEE]
0.0
2.0
4.0
6.0
8.0
10.0
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
WLPcrit-Write
WLPcrit-Read
Time (ns)
Supply Voltage (V)
Write Assist(WA) Disabled
WA Enabled
VDD rise of internal node voltage is due to the non-saturating I D (V DS ) of TFETs.
The negative bitline (NBL) seems to be best suited for TFET SRAM cells in order
to reduce VDD and maintain speed. TFETs used for implementation have V OF F
voltage of 150 mV as described in Chap. 2. Because of very-low leakage current
in TFETs for V GS < V OF F , the power consumption penalty and stability issue of
WD cells is negligible with negative bitline write assist down to −150 mV. With
150 mV negative bitline, 79.2% to 54.7% performance improvement was achieved
for a supply voltage range from 0.6 V to 0.9 V, respectively. Without write assist
WLPcrit for write is more than 40 ns for a supply below 0.6 V while with write
assist enabled WLPcrit is less than 17 ns at 0.5 V supply voltage. Above 0.9 V supply
voltage WLPcrit is less than 1 ns with write assist disabled (see Fig. 3.15).
3.3.6 8T-TFET SRAM Stability and Performance
The performance and stability of the 8T dual-port TFET SRAM was analyzed for
a range of supply voltages for applying DVFS. Figure 3.16 shows the WLPcrit for
write and read operation of the designed 32 Kb memory; in order to keep the delay
at reasonable values Write-Assist (WA) techniques are applied if VDD is lowered
below 0.9 V. The achieved WLPcrit for read and write at 1 V supply is 681 ps and
377 ps, respectively.
Figure 3.17 shows the RSNM and WSNM for different supply voltages. The
achieved noise-margin values at 1 V supply are 114 mV for RSNM and 185 mV
for WSNM. An improvement of approximately 5× and 8× in RSNM and WSNM,
respectively, is observed in comparison to computed margins for a standard 6T
TFET SRAM cell with outward access transistors in the balanced case [31]. The
achieved RSNM and WSNM are sufficient for supply voltages of 1 V and above.
At lower voltages noise margins can be increased by applying assist techniques for
read and write resulting in higher RSNM and WSNM, which enable the use of long
wordlines with bit interleaving without any HS problem. In a TFET the leakage