30
3 SRAMs
the BLR voltage by 150 mV is 377 ps at 1 V supply. This results in less than 1ns
read cycle time. Single-ended sensing with long bitlines or open bitline architecture
with split bitlines can be used for sensing depending on the memory architecture
choice. The next section describes both of these single-ended sensing schemes.
3.3.4 Single-Ended Sensing Methods
In order to optimize the TFET cells single-ended sensing is used in our designs.
Single-ended sensing has already been reported in literature [51–53]. Single-ended
sensing can be done using a differential sense amplifier with a reference voltage
source or with inverter-based sensing. In the case of inverter-based sensing, the
bitline needs to be discharged fully resulting in slow operation. In [52], an inverterbased sense keeper is implemented in the read circuit to improve the read speed.
After analyzing various single-ended sensing methods we designed single-ended
sensing using an imbalanced differential sense amplifier based on charge injection.
Our design uses charge injection to create the imbalance for removing the reference
voltage source and symmetric sizing of devices for minimizing variations. The
proposed sensing technique used in this SRAM is presented in Chap. 7, Sect. 7.2.
3.3.5 Write Operation
In order to perform the write operation in the proposed 8T cell, see Fig. 3.11, both
WL1 and WL2 are set high. Depending on the value to be written, either BLW1
or BLW2 is pulled down to GND and the other remains at the retention voltage,
i.e., 0.6 V. Also, the BLR corresponding to the same wordline as the BLW, which is
pulled down remains high, and the other BLR is set to 0.4 V. For instance, in order
to write a “1” at node V1 in the cell, BLW1 is 0 V, BLW2 is 0.6 V, BLR1 is VDD,
and BLR2 is 0.4 V. Figure 3.14 shows the write waveform in the cell. BLR and BLW
for HS cells are at the retention voltage. This configuration of voltages on bitlines
ensures that the TFET pass transistors have minimum leakage for HS and WD cells.
Contrary to the typical 6T-TFET single-port SRAM cell, in our 8T cell no transfer
transistor is reverse biased close to the turn-on of the p-i-n diode in the memory
active mode resulting in no impact of WD cells on performance, stability, and
leakage. The analysis of different write-assist techniques for TFET cells shows that
WL boosting reduces noise margins in HS cells, which are in read mode. Write
time increases drastically with supply under-drive (Vddud) for TFET SRAM cells
because of the steep subthreshold slope of TFETs and non-saturating I D (V DS )
dependence. The write margin also limits the minimum operating voltage. The
TFET pull-up in the SRAM cell is very weak at lower voltages and takes much
longer to charge the memory cell node resulting in a very long critical wordline
pulse width (WLPcrit) requirement for a successful write. A comparison of WLPcrit
3 SRAMs
the BLR voltage by 150 mV is 377 ps at 1 V supply. This results in less than 1ns
read cycle time. Single-ended sensing with long bitlines or open bitline architecture
with split bitlines can be used for sensing depending on the memory architecture
choice. The next section describes both of these single-ended sensing schemes.
3.3.4 Single-Ended Sensing Methods
In order to optimize the TFET cells single-ended sensing is used in our designs.
Single-ended sensing has already been reported in literature [51–53]. Single-ended
sensing can be done using a differential sense amplifier with a reference voltage
source or with inverter-based sensing. In the case of inverter-based sensing, the
bitline needs to be discharged fully resulting in slow operation. In [52], an inverterbased sense keeper is implemented in the read circuit to improve the read speed.
After analyzing various single-ended sensing methods we designed single-ended
sensing using an imbalanced differential sense amplifier based on charge injection.
Our design uses charge injection to create the imbalance for removing the reference
voltage source and symmetric sizing of devices for minimizing variations. The
proposed sensing technique used in this SRAM is presented in Chap. 7, Sect. 7.2.
3.3.5 Write Operation
In order to perform the write operation in the proposed 8T cell, see Fig. 3.11, both
WL1 and WL2 are set high. Depending on the value to be written, either BLW1
or BLW2 is pulled down to GND and the other remains at the retention voltage,
i.e., 0.6 V. Also, the BLR corresponding to the same wordline as the BLW, which is
pulled down remains high, and the other BLR is set to 0.4 V. For instance, in order
to write a “1” at node V1 in the cell, BLW1 is 0 V, BLW2 is 0.6 V, BLR1 is VDD,
and BLR2 is 0.4 V. Figure 3.14 shows the write waveform in the cell. BLR and BLW
for HS cells are at the retention voltage. This configuration of voltages on bitlines
ensures that the TFET pass transistors have minimum leakage for HS and WD cells.
Contrary to the typical 6T-TFET single-port SRAM cell, in our 8T cell no transfer
transistor is reverse biased close to the turn-on of the p-i-n diode in the memory
active mode resulting in no impact of WD cells on performance, stability, and
leakage. The analysis of different write-assist techniques for TFET cells shows that
WL boosting reduces noise margins in HS cells, which are in read mode. Write
time increases drastically with supply under-drive (Vddud) for TFET SRAM cells
because of the steep subthreshold slope of TFETs and non-saturating I D (V DS )
dependence. The write margin also limits the minimum operating voltage. The
TFET pull-up in the SRAM cell is very weak at lower voltages and takes much
longer to charge the memory cell node resulting in a very long critical wordline
pulse width (WLPcrit) requirement for a successful write. A comparison of WLPcrit