3.3 Dual-Port SRAM Architecture
27
Fig. 3.10 Block diagram of
proposed dual-port
scratchpad [©2015 IEEE]
Data In1
Data Out1
Ready1
WE1
Clock
Data In2
Data Out2
Ready2
WE2
Addr 1
Addr 2
application. The design of the pseudo dual-port scratchpad is optimized for both
speed and power. SRAM arrays are major contributors to overall leakage power consumption and, contrary to peripheral circuits, can never be power gated; therefore, in
order to limit leakage the memory cells are designed using TFETs. However, TFETs
have low current drive and high capacitance as compared to CMOS and therefore,
they take more time to charge-discharge the nodes and consume more switching
power. In order to optimize speed and power, logic and drivers for high-capacitance
nodes with high switching activity are designed with CMOS. Thus, all the periphery
circuits such as WL drivers and sense amplifiers, which have greater switching
activity are designed with CMOS at the cost of increased leakage. Since CMOS
is having more current drive as compared to TFETs, CMOS drivers are smaller in
size for a given speed specification.
Figure 3.10 shows the block diagram of the proposed scratchpad using DPSRAM
with both ports having read and write feature. In the proposed design, two
simultaneous read or a single write on either port is supported. This is done to
optimize the cell because the number of reads are significantly larger than the
number of writes in a DPSRAM used as scratchpad for embedded processors; for
DSP applications such as video decoding, once the frame is decoded and saved
in the SRAM buffer, the same frame buffer may be read several times for motion
estimation, predictions and to compute other frames. For this purpose, the proposed
scratchpad design has a “Ready” signal per port to notify that memory is ready to
accept a new read or write operation. Since a single write is allowed, if a write is
ongoing on port-1, the “ready” signal on port-2 will be “0” to notify the processor
that the memory is busy.
3.3.1 Dual-Port TFET SRAM Cell
The proposed TFET DPSRAM cell [50] is shown in Fig. 3.11; it has two wordlines
(WL1 and WL2), two bitlines (BLR1 and BLR2) used for read and write, and two
bitlines (BLW1 and BLW2) used for write. A single-ended read scheme is applied
27
Fig. 3.10 Block diagram of
proposed dual-port
scratchpad [©2015 IEEE]
Data In1
Data Out1
Ready1
WE1
Clock
Data In2
Data Out2
Ready2
WE2
Addr 1
Addr 2
application. The design of the pseudo dual-port scratchpad is optimized for both
speed and power. SRAM arrays are major contributors to overall leakage power consumption and, contrary to peripheral circuits, can never be power gated; therefore, in
order to limit leakage the memory cells are designed using TFETs. However, TFETs
have low current drive and high capacitance as compared to CMOS and therefore,
they take more time to charge-discharge the nodes and consume more switching
power. In order to optimize speed and power, logic and drivers for high-capacitance
nodes with high switching activity are designed with CMOS. Thus, all the periphery
circuits such as WL drivers and sense amplifiers, which have greater switching
activity are designed with CMOS at the cost of increased leakage. Since CMOS
is having more current drive as compared to TFETs, CMOS drivers are smaller in
size for a given speed specification.
Figure 3.10 shows the block diagram of the proposed scratchpad using DPSRAM
with both ports having read and write feature. In the proposed design, two
simultaneous read or a single write on either port is supported. This is done to
optimize the cell because the number of reads are significantly larger than the
number of writes in a DPSRAM used as scratchpad for embedded processors; for
DSP applications such as video decoding, once the frame is decoded and saved
in the SRAM buffer, the same frame buffer may be read several times for motion
estimation, predictions and to compute other frames. For this purpose, the proposed
scratchpad design has a “Ready” signal per port to notify that memory is ready to
accept a new read or write operation. Since a single write is allowed, if a write is
ongoing on port-1, the “ready” signal on port-2 will be “0” to notify the processor
that the memory is busy.
3.3.1 Dual-Port TFET SRAM Cell
The proposed TFET DPSRAM cell [50] is shown in Fig. 3.11; it has two wordlines
(WL1 and WL2), two bitlines (BLR1 and BLR2) used for read and write, and two
bitlines (BLW1 and BLW2) used for write. A single-ended read scheme is applied