26
3 SRAMs
BLL
(VDD)
BLR
(0.6V/GND)
V1
V2
WL1
WL1
WL2
WL2
VDD
GND
TR1
TR2
TR3
TR4
DR1
DR2
LD1
LD2
Fig. 3.9 8T-TFET dual-wordline bitcell [©2012 IEEE]
3.3 Dual-Port SRAM Architecture
DPSRAMs provide simultaneous access to a single static SRAM memory from
two buses with full synchronous operation on both ports. In embedded systems
the use of dual-port memories is increasing in order to optimize area, power, and
throughput requirements. As an example, dual-port SRAMs are used as buffers
in DSP processors [46]. Multi-port SRAMs are used as scratchpads to provide
independent memory access to each core while using shared memory resources
[47, 48]. With increasing demand for performance and feature size shrinking, power
consumption in SRAMs is rising. This problem is critical in DPSRAMs due to the
added complexity in the cell. In a standard 8T-CMOS dual-port SRAM [46] cells
need to be larger to get the same stability as single-port SRAM, because in a worstcase situation two read operations can occur on the same row. This event results in
a 2× current drive increase of the pass transistor reducing the RSNM and requiring
the increase of the SRAM cell size to improve stability. In [47], write assist is
used to reduce the minimum supply voltage required for correct operation. Another
common method used to optimize power for different performance requirements in
DPSRAMs is Dynamic Voltage Frequency Scaling (DVFS) [49]. However, DVFS
only partially addresses the leakage power consumption in SRAMs as leakage
power is the dominant part in the overall power consumption. Thus, optimization
at cell and/or architecture level is required for achieving low leakage and power
efficiency. A 15 µA/Mb leakage is reported at 0.7 V supply in 45 nm CMOS in [49],
and in [8], the authors propose a 6T-SRAM cell of 2.159 µm 2 using long-channel
and thick-oxide devices; with the application of reverse back-bias (RBB) during
standby authors report over 10 3 × leakage reduction (27 fA/bit) at room temperature
as compared to a standard SRAM design.
The following section presents a TFET-based 8T-Dual-Port SRAM cell [50] and
TFET/CMOS hybrid memory architecture with ultra-low leakage for scratchpad
3 SRAMs
BLL
(VDD)
BLR
(0.6V/GND)
V1
V2
WL1
WL1
WL2
WL2
VDD
GND
TR1
TR2
TR3
TR4
DR1
DR2
LD1
LD2
Fig. 3.9 8T-TFET dual-wordline bitcell [©2012 IEEE]
3.3 Dual-Port SRAM Architecture
DPSRAMs provide simultaneous access to a single static SRAM memory from
two buses with full synchronous operation on both ports. In embedded systems
the use of dual-port memories is increasing in order to optimize area, power, and
throughput requirements. As an example, dual-port SRAMs are used as buffers
in DSP processors [46]. Multi-port SRAMs are used as scratchpads to provide
independent memory access to each core while using shared memory resources
[47, 48]. With increasing demand for performance and feature size shrinking, power
consumption in SRAMs is rising. This problem is critical in DPSRAMs due to the
added complexity in the cell. In a standard 8T-CMOS dual-port SRAM [46] cells
need to be larger to get the same stability as single-port SRAM, because in a worstcase situation two read operations can occur on the same row. This event results in
a 2× current drive increase of the pass transistor reducing the RSNM and requiring
the increase of the SRAM cell size to improve stability. In [47], write assist is
used to reduce the minimum supply voltage required for correct operation. Another
common method used to optimize power for different performance requirements in
DPSRAMs is Dynamic Voltage Frequency Scaling (DVFS) [49]. However, DVFS
only partially addresses the leakage power consumption in SRAMs as leakage
power is the dominant part in the overall power consumption. Thus, optimization
at cell and/or architecture level is required for achieving low leakage and power
efficiency. A 15 µA/Mb leakage is reported at 0.7 V supply in 45 nm CMOS in [49],
and in [8], the authors propose a 6T-SRAM cell of 2.159 µm 2 using long-channel
and thick-oxide devices; with the application of reverse back-bias (RBB) during
standby authors report over 10 3 × leakage reduction (27 fA/bit) at room temperature
as compared to a standard SRAM design.
The following section presents a TFET-based 8T-Dual-Port SRAM cell [50] and
TFET/CMOS hybrid memory architecture with ultra-low leakage for scratchpad