3.2 TFET SRAMs - State of the Art
25
order to not disturb the data in the cell a read should be done with low read currents
in pA range resulting in very slow operation.
In summary, all the above-mentioned published TFET SRAMs revealed difficulties in obtaining sufficient stability in read and write operations. As the stability
in both operation modes is inherently low due to the electrical performance of
TFETs and the low supply voltage, it is difficult for circuit designers to find the best
balance between read and write. Moreover, due to the unidirectional TFET behavior
researchers were forced to target very low-V DD operation resulting in even larger
difficulty in achieving sufficient stability margins in active mode. New architectural
solutions were developed to improve the single-cell stability but the proposed cells
in [30, 31] suffer from HS and a special case of WD when organized as an array
of memory cells. Similar to TFET SRAMs, overcoming HS in CMOS SRAMs is
particularly important for 8T CMOS cells with full separation of read and write
mechanisms.
Two solutions were proposed in literature for the 8T CMOS SRAM: (1) all
bits on the selected wordline must be spatially adjacent (no bit interleaving) with
the wordline length covering only these bits [39] and (2) the implementation of a
column-based write-back mechanism [40, 41]. These solutions could be applied to
TFET SRAMs also, but they will result in an area penalty and in additional design
and operation complexity. Additional operation and design complexity should be
avoided for devices with rather poor dynamic performance such as TFETs. In
addition, the design with no bit interleaving does not allow the application of
conventional Error Correction Codes (ECC), which is essential to handle soft errors
[42]. It should be noted that the Soft-Error Rate (SER) increases significantly under
scaled-down V DD operation [43], which is commonly used in TFET-based designs
to avoid high current due to the turn-on of the p-i-n diode with high reverse-biased
V DS . As shown in [44, 45], TFETs are better in terms of soft-error rate; however, for
circuits with both CMOS and TFETs the soft-error rate increases with scaling down
the supply voltage. This necessitates the application of an efficient ECC scheme
resulting in further increase in design overhead, complexity, and area. In [39], the
authors propose a long column for write (512 cells) with the advantage of a short
wordline in designs with no bit interleaving. This choice can cause a number of
issues in TFET designs due to the WD problem. An 8T-TFET SRAM with dual
wordlines and consuming two clock cycles for writing a single word, which is HS
and WD-free at the cost of higher area (similar to a dual-port memory) is presented
in [32]. As shown in Fig. 3.9, the bitcell is designed such that none of the TFETs
experiences a high reverse-biased V DS . The advantage of this cell is that it can
provide low-leakage operation at high supply voltages. This circuit is free from
HS and WD issues at the cost of dual wordlines and three supply voltage levels. In
addition, both “0”s and “1”s cannot be written at the same time in the memory array
and need two write cycles for storing one word.
25
order to not disturb the data in the cell a read should be done with low read currents
in pA range resulting in very slow operation.
In summary, all the above-mentioned published TFET SRAMs revealed difficulties in obtaining sufficient stability in read and write operations. As the stability
in both operation modes is inherently low due to the electrical performance of
TFETs and the low supply voltage, it is difficult for circuit designers to find the best
balance between read and write. Moreover, due to the unidirectional TFET behavior
researchers were forced to target very low-V DD operation resulting in even larger
difficulty in achieving sufficient stability margins in active mode. New architectural
solutions were developed to improve the single-cell stability but the proposed cells
in [30, 31] suffer from HS and a special case of WD when organized as an array
of memory cells. Similar to TFET SRAMs, overcoming HS in CMOS SRAMs is
particularly important for 8T CMOS cells with full separation of read and write
mechanisms.
Two solutions were proposed in literature for the 8T CMOS SRAM: (1) all
bits on the selected wordline must be spatially adjacent (no bit interleaving) with
the wordline length covering only these bits [39] and (2) the implementation of a
column-based write-back mechanism [40, 41]. These solutions could be applied to
TFET SRAMs also, but they will result in an area penalty and in additional design
and operation complexity. Additional operation and design complexity should be
avoided for devices with rather poor dynamic performance such as TFETs. In
addition, the design with no bit interleaving does not allow the application of
conventional Error Correction Codes (ECC), which is essential to handle soft errors
[42]. It should be noted that the Soft-Error Rate (SER) increases significantly under
scaled-down V DD operation [43], which is commonly used in TFET-based designs
to avoid high current due to the turn-on of the p-i-n diode with high reverse-biased
V DS . As shown in [44, 45], TFETs are better in terms of soft-error rate; however, for
circuits with both CMOS and TFETs the soft-error rate increases with scaling down
the supply voltage. This necessitates the application of an efficient ECC scheme
resulting in further increase in design overhead, complexity, and area. In [39], the
authors propose a long column for write (512 cells) with the advantage of a short
wordline in designs with no bit interleaving. This choice can cause a number of
issues in TFET designs due to the WD problem. An 8T-TFET SRAM with dual
wordlines and consuming two clock cycles for writing a single word, which is HS
and WD-free at the cost of higher area (similar to a dual-port memory) is presented
in [32]. As shown in Fig. 3.9, the bitcell is designed such that none of the TFETs
experiences a high reverse-biased V DS . The advantage of this cell is that it can
provide low-leakage operation at high supply voltages. This circuit is free from
HS and WD issues at the cost of dual wordlines and three supply voltage levels. In
addition, both “0”s and “1”s cannot be written at the same time in the memory array
and need two write cycles for storing one word.