22
3 SRAMs
Fig. 3.4 8T-TFET bitcells
[©2011 IEEE]
VDD
NPDL
NRD
NPDR
AXL
AXR
GND
RWLB
WBL
RBL
WBLB
PPUR
PPUL
WWL
WWL
Fig. 3.5 7T-TFET bitcell [©2011 IEEE]
high and a “1” and “0” are written using M5 and M6, respectively. Since both
writes are done using NTFETs, this results in an asymmetric write performance
and stability. In addition, the issue of WD cells is still valid creating problems using
this cell in a memory array. Therefore, the operating voltage is limited for this cell
as well.