20
3 SRAMs
WD
HS
RET
ACC
HS
WD
BL[0]=GND→VDD
BLB[0]=GND
BL[1]=GND
BLB[1]=VDD
BL[2]=GND→VDD
BLB[2]=GND
WL[1]=VDD
WL[0]=GND
WL[2]=GND
ITR_LEAK
‘0'
IREAD
IWRITE
ITR_LEAK
ITR_LEAK
‘1'
‘0'
‘1'
IREAD
RET
RET
RET
‘0'
‘1'
‘0'
‘1'
‘0'
‘1'
Fig. 3.2 3 × 3 bitcell array showing HS and WD problem
a number of constraints on the SRAM design. First, when sizing the cell and
evaluating the stability, one has to maintain sufficient read-stability of the 6T cell
core structure. In the design of TFET SRAMs HS can be an issue due to the initially
low RSNM and WSNM values.
In literature, various circuit techniques are proposed for addressing these issues
[26, 30–32]. However, these techniques require additional silicon area and increase
the design and operation complexity. Furthermore, application of these techniques
in TFET SRAMs is particularly challenging due to the device poor dynamic
performance further contributing to the already low speed of TFET memories.
3.2.1.2.3 Write-Disturb (WD) Problem
The Write-Disturb problem is caused by leaky cells in the bitcell array during write
operation. As shown in Fig. 3.3 for a 3 × 3 TFET bitcell array, the top- and bottomrow bitcells can be highly leaky depending on the bitcell data and bitline voltages
while writing the center row. The leakage is due to high reverse-biased V DS on the
access transistors on the bitlines, which are at VDD during write operation. In our
simulations a 32 nA bitcell leakage is measured at 1 V supply voltage. In the worstcase WD in a 1 Kb bitcell array with 32-bit words, where all the cells are leaky
except the word being written, a 30 µA ((1024 − 32) ∗ 32 nA) leakage current is
consumed.
In order to reduce the leakage caused by WD, supply voltages are limited to
ultra-low values of less than 0.3 V. However, at such low voltages lower performance
(read/write) and stability of bitcells become an issue. The following section presents
a summary of circuits proposed to address the above issues of TFET SRAMs.
3 SRAMs
WD
HS
RET
ACC
HS
WD
BL[0]=GND→VDD
BLB[0]=GND
BL[1]=GND
BLB[1]=VDD
BL[2]=GND→VDD
BLB[2]=GND
WL[1]=VDD
WL[0]=GND
WL[2]=GND
ITR_LEAK
‘0'
IREAD
IWRITE
ITR_LEAK
ITR_LEAK
‘1'
‘0'
‘1'
IREAD
RET
RET
RET
‘0'
‘1'
‘0'
‘1'
‘0'
‘1'
Fig. 3.2 3 × 3 bitcell array showing HS and WD problem
a number of constraints on the SRAM design. First, when sizing the cell and
evaluating the stability, one has to maintain sufficient read-stability of the 6T cell
core structure. In the design of TFET SRAMs HS can be an issue due to the initially
low RSNM and WSNM values.
In literature, various circuit techniques are proposed for addressing these issues
[26, 30–32]. However, these techniques require additional silicon area and increase
the design and operation complexity. Furthermore, application of these techniques
in TFET SRAMs is particularly challenging due to the device poor dynamic
performance further contributing to the already low speed of TFET memories.
3.2.1.2.3 Write-Disturb (WD) Problem
The Write-Disturb problem is caused by leaky cells in the bitcell array during write
operation. As shown in Fig. 3.3 for a 3 × 3 TFET bitcell array, the top- and bottomrow bitcells can be highly leaky depending on the bitcell data and bitline voltages
while writing the center row. The leakage is due to high reverse-biased V DS on the
access transistors on the bitlines, which are at VDD during write operation. In our
simulations a 32 nA bitcell leakage is measured at 1 V supply voltage. In the worstcase WD in a 1 Kb bitcell array with 32-bit words, where all the cells are leaky
except the word being written, a 30 µA ((1024 − 32) ∗ 32 nA) leakage current is
consumed.
In order to reduce the leakage caused by WD, supply voltages are limited to
ultra-low values of less than 0.3 V. However, at such low voltages lower performance
(read/write) and stability of bitcells become an issue. The following section presents
a summary of circuits proposed to address the above issues of TFET SRAMs.