3.2 TFET SRAMs - State of the Art
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(transfer and load transistors) in both operation modes. This means that the same
transistor pair should allow at the same time to pull down the internal storage node
to GND during write, and disallow this node to discharge during read. As a result,
in the 6T-TFET SRAM design, contrary to the 6T-CMOS SRAM, it is impossible
to optimize read and write stabilities separately. Therefore, a compromise between
the two has to be found.
3.2.1.1 Stability
The metric used typically to characterize SRAM stability is the Static Noise Margin
(SNM). Similar to Kim’s data [31], the obtained Read SNM (RSNM) and Write
SNM (WSNM) have values around 30 mV with optimum sizing of the cell. Such
low values of noise margins are unacceptable and for this reason Kim suggested to
resize the cell with a low sizing ratio (PU), pull-up (LD1/LD2) to access transistor
(TR1/TR2), in order to optimize for write stability and use an extra transistor. The
comparison of RSNM and WSNM of the bitcell as a function of the PU with the
driver-NTFET size kept constant at V DD = 1 V is also presented. We show in the
following section that unless certain architecture-level techniques are applied, this
solution has several issues that are difficult to overcome if the analysis framework
is enlarged and the TFET SRAM cell is placed in a memory array.
3.2.1.2 Array-Based 6T TFET SRAM Analysis
3.2.1.2.1 Introduction
Figure 3.2 depicts a nine-cell fragment of a TFET SRAM array. In the middle of this
fragment is the cell accessed for write, ACC. The corner cells RET are in retention
with both bitlines and the wordline set to “0.” The HS cells, Half-Selected cells
are connected to the same row as the written cell and are in read mode. The WD
cells connected to the same column as the written cell, are under Write-Disturb with
the wordline set to GND, one of the bitlines set to “1” and the other bitline set to
“0.” Left and right columns indexed “0” and “2,” respectively, have bitlines initially
precharged to GND and floated with BL[0] and BL[2] being slowly pulled up by HS
cells due to “1” being stored on the left node of these cells. BL[1] and BLB[1] are
connected to GND and VDD, respectively, to ensure a correct write of the “ACC”
cell.
3.2.1.2.2 Half-Selection (HS) Problem
The problem of half-selection is a known issue for CMOS SRAM design. It consists
in the cells on the same wordline as the one accessed for write being in the read
condition with both bitlines precharged at VDD or GND and floated. This sets
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(transfer and load transistors) in both operation modes. This means that the same
transistor pair should allow at the same time to pull down the internal storage node
to GND during write, and disallow this node to discharge during read. As a result,
in the 6T-TFET SRAM design, contrary to the 6T-CMOS SRAM, it is impossible
to optimize read and write stabilities separately. Therefore, a compromise between
the two has to be found.
3.2.1.1 Stability
The metric used typically to characterize SRAM stability is the Static Noise Margin
(SNM). Similar to Kim’s data [31], the obtained Read SNM (RSNM) and Write
SNM (WSNM) have values around 30 mV with optimum sizing of the cell. Such
low values of noise margins are unacceptable and for this reason Kim suggested to
resize the cell with a low sizing ratio (PU), pull-up (LD1/LD2) to access transistor
(TR1/TR2), in order to optimize for write stability and use an extra transistor. The
comparison of RSNM and WSNM of the bitcell as a function of the PU with the
driver-NTFET size kept constant at V DD = 1 V is also presented. We show in the
following section that unless certain architecture-level techniques are applied, this
solution has several issues that are difficult to overcome if the analysis framework
is enlarged and the TFET SRAM cell is placed in a memory array.
3.2.1.2 Array-Based 6T TFET SRAM Analysis
3.2.1.2.1 Introduction
Figure 3.2 depicts a nine-cell fragment of a TFET SRAM array. In the middle of this
fragment is the cell accessed for write, ACC. The corner cells RET are in retention
with both bitlines and the wordline set to “0.” The HS cells, Half-Selected cells
are connected to the same row as the written cell and are in read mode. The WD
cells connected to the same column as the written cell, are under Write-Disturb with
the wordline set to GND, one of the bitlines set to “1” and the other bitline set to
“0.” Left and right columns indexed “0” and “2,” respectively, have bitlines initially
precharged to GND and floated with BL[0] and BL[2] being slowly pulled up by HS
cells due to “1” being stored on the left node of these cells. BL[1] and BLB[1] are
connected to GND and VDD, respectively, to ensure a correct write of the “ACC”
cell.
3.2.1.2.2 Half-Selection (HS) Problem
The problem of half-selection is a known issue for CMOS SRAM design. It consists
in the cells on the same wordline as the one accessed for write being in the read
condition with both bitlines precharged at VDD or GND and floated. This sets