18
3 SRAMs
3.2 TFET SRAMs - State of the Art
3.2.1 6T-TFET SRAM Design
The operation of the typical CMOS 6T-SRAM in active modes is depicted in
Fig. 3.1a, b. In CMOS the read and write mechanisms can be optimized separately
by tuning the corresponding transistor ratios, [35], due to the bidirectional current
flow in the access transistors, see Fig. 3.1a, b. In a TFET SRAM the transfer
transistors are unidirectional.
The 6T-TFET SRAM operation with outward transfer n-type transistors, as
presented in [31], is depicted in Fig. 3.1c, d. Arrows in the TFET symbol show the
direction of the forward current flow and hence point at the position of the source,
see Fig. 2.16, Chap. 2. In read both bitlines are precharged at GND and the current
flowing from the cell pulls up the bitline on the side storing a “1,” thus creating a
voltage difference V between the bitlines. During write, the bitline BLR on the
side of the node V2 being set to “1” is pulled up to VDD. In this situation, while
node V1 is pulled down by bitline BLL to GND, the reverse-biased TR2 current
I leak which is high enough, for V DS = −V DD, to contribute in completing the
write operation by flipping the cell through positive feedback. Contrary to the typical
CMOS SRAM, in a TFET memory the current flows through the same transistor pair
BLL (VDD)
BLR (VDD-ΔV)
WL
WL
VDD
GND
TR1
TR2
DR1
DR2
LD1
LD2
V1=“1”
V2=”0"
I read
BLL (GND)
BLR (VDD)
WL
WL
VDD
GND
TR1
TR2
DR1
DR2
LD1
LD2
V1=“1”
V2=”0"
I write
I read
BLL (GND+ΔV)
BLR (GND)
WL
WL
VDD
GND
TR1
TR2
DR1
DR2
LD1
LD2
V1=“1”
V2=”0"
I read
BLL (GND)
BLR (VDD)
WL
WL
VDD
GND
TR1
TR2
DR1
DR2
LD1
LD2
V1=“1”
V2=”0"
I write
I leak
a.
b.
c.
d.
Fig. 3.1 Typical bulk CMOS 6T-SRAM operation during read, (a) and write (b); the TFET 6TSRAM operation during read (c) and write (d) [©2009 IEEE]