Chapter 3
SRAMs
3.1 Introduction
The TFET emerges as one of the promising alternatives to CMOS to design
ultra-low power memories due to very-low leakage current [4, 5, 14, 26, 30–33].
In literature, reports on optimizing TFET circuits are mainly focused on SRAM
designs with the aim to reduce leakage [26, 30–32].
The key challenge in designing TFET-based SRAMs or CAMs is linked to the
different-than-CMOS TFET characteristics, i.e., unidirectionality, higher dependence I D (V DS ) in saturation and lower I ON than CMOS [34], resulting in a
high degree of difficulty in maintaining a balance between stable read and write
operations [26, 30, 31], and achieving sufficiently low access times. Therefore,
TFET SRAM designs have to be investigated in-depth in order to optimize area,
stability, and performance.
This chapter analyzes the applicability of TFETs in LSTP applications for
longer battery life and/or energy harvesting. Section 3.2 presents the state of the
art of TFET SRAM designs covering performance characteristics followed by an
overview of different cell topologies. Architecture issues at the memory-array level
in known TFET memory designs are analyzed and proposed solutions are reviewed.
Section 3.3 describes a Dual-Port SRAM (DPSRAM) memory architecture using
an 8T-TFET Dual-Port SRAM bitcell, which overcomes array-level robustness
issues (Half-Selection (HS) and Write-Disturb (WD) problems). A detailed analysis
of the performance in read and write is presented including stability and response
time.
Section 3.4 introduces a 3T-TFET SRAM bitcell and a TFET-CMOS hybrid
SRAM memory architecture based on this cell. The detailed operation and performance are described and the physical implementation is outlined. A hybrid
128*64 bit array is analyzed and shown to have superior performance compared
to a CMOS memory of the same size.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_3
17
SRAMs
3.1 Introduction
The TFET emerges as one of the promising alternatives to CMOS to design
ultra-low power memories due to very-low leakage current [4, 5, 14, 26, 30–33].
In literature, reports on optimizing TFET circuits are mainly focused on SRAM
designs with the aim to reduce leakage [26, 30–32].
The key challenge in designing TFET-based SRAMs or CAMs is linked to the
different-than-CMOS TFET characteristics, i.e., unidirectionality, higher dependence I D (V DS ) in saturation and lower I ON than CMOS [34], resulting in a
high degree of difficulty in maintaining a balance between stable read and write
operations [26, 30, 31], and achieving sufficiently low access times. Therefore,
TFET SRAM designs have to be investigated in-depth in order to optimize area,
stability, and performance.
This chapter analyzes the applicability of TFETs in LSTP applications for
longer battery life and/or energy harvesting. Section 3.2 presents the state of the
art of TFET SRAM designs covering performance characteristics followed by an
overview of different cell topologies. Architecture issues at the memory-array level
in known TFET memory designs are analyzed and proposed solutions are reviewed.
Section 3.3 describes a Dual-Port SRAM (DPSRAM) memory architecture using
an 8T-TFET Dual-Port SRAM bitcell, which overcomes array-level robustness
issues (Half-Selection (HS) and Write-Disturb (WD) problems). A detailed analysis
of the performance in read and write is presented including stability and response
time.
Section 3.4 introduces a 3T-TFET SRAM bitcell and a TFET-CMOS hybrid
SRAM memory architecture based on this cell. The detailed operation and performance are described and the physical implementation is outlined. A hybrid
128*64 bit array is analyzed and shown to have superior performance compared
to a CMOS memory of the same size.
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_3
17