2.3 TFET Power and Delay Comparison with CMOS
13
Time (ns)
-0.4
21.8
23.8
25.8
27.8
29.8
31.8
33.8
1.2
0.8
0.4
0.0
1.6
RO Output (V)
CMOS
TFET
TFET low C GD
Fig. 2.13 The result of the nine-stage RO simulation performed using TFETs at V DD = 1 V
[©2016 IEEE]
additional factor contributing to the higher TFET PDP is linked to its larger Miller
capacitance than that of CMOS [29], which should be as low as possible for highspeed operation of the RO. The high value of the Miller capacitance at each RO node
lengthens the switching time and leads to high under- and overshoots in the output
voltage, see Fig. 2.13. The impact of the Miller capacitance effect is demonstrated
by simulating the TFET RO also with a fixed gate to drain capacitance (C GD ) of
0.114 fF/µm, which is the minimum C GD value extracted from TCAD simulations
of our device. By imposing a fixed low value of C GD the effect of Miller capacitance
is minimized. Figure 2.11 shows that with a fixed C GD the TFET RO frequency is 8x
higher than that of the actual TFET RO. The Miller capacitance impact on PDP can
be seen in Fig. 2.12 where it can be observed that TFETs with low Miller capacitance
outperform CMOS. Figure 2.13 compares waveforms for TFET ROs with variable
f (V DS ) and fixed low C GD with CMOS RO; the under- and overshoots for the
TFET RO with fixed C GD are 3× smaller and the RO frequency is 8× higher. In
summary, we can conclude that the TFET lower dynamic performance is linked to
three key properties of this device: (1) high Miller capacitance value, (2) low I ON ,
and (3) strong I ON dependency on V DS (non-saturating), see Fig. 2.8. This leads to
low frequency operation because of the difficulty in fully charging and discharging
the large capacitances of RO nodes.
Reports in literature show hetero-junction TFETs having higher performance.
However, designing reliable hetero-junction TFETs is much more difficult due to
process immaturity in comparison to Si-TFETs, which can be implemented using a
process similar to Si-CMOS. This work focuses on the design of Si-TFET integrated
circuits for applications where these circuits outperform CMOS and the combination
of the two achieves both performance and power savings on the same chip.
13
Time (ns)
-0.4
21.8
23.8
25.8
27.8
29.8
31.8
33.8
1.2
0.8
0.4
0.0
1.6
RO Output (V)
CMOS
TFET
TFET low C GD
Fig. 2.13 The result of the nine-stage RO simulation performed using TFETs at V DD = 1 V
[©2016 IEEE]
additional factor contributing to the higher TFET PDP is linked to its larger Miller
capacitance than that of CMOS [29], which should be as low as possible for highspeed operation of the RO. The high value of the Miller capacitance at each RO node
lengthens the switching time and leads to high under- and overshoots in the output
voltage, see Fig. 2.13. The impact of the Miller capacitance effect is demonstrated
by simulating the TFET RO also with a fixed gate to drain capacitance (C GD ) of
0.114 fF/µm, which is the minimum C GD value extracted from TCAD simulations
of our device. By imposing a fixed low value of C GD the effect of Miller capacitance
is minimized. Figure 2.11 shows that with a fixed C GD the TFET RO frequency is 8x
higher than that of the actual TFET RO. The Miller capacitance impact on PDP can
be seen in Fig. 2.12 where it can be observed that TFETs with low Miller capacitance
outperform CMOS. Figure 2.13 compares waveforms for TFET ROs with variable
f (V DS ) and fixed low C GD with CMOS RO; the under- and overshoots for the
TFET RO with fixed C GD are 3× smaller and the RO frequency is 8× higher. In
summary, we can conclude that the TFET lower dynamic performance is linked to
three key properties of this device: (1) high Miller capacitance value, (2) low I ON ,
and (3) strong I ON dependency on V DS (non-saturating), see Fig. 2.8. This leads to
low frequency operation because of the difficulty in fully charging and discharging
the large capacitances of RO nodes.
Reports in literature show hetero-junction TFETs having higher performance.
However, designing reliable hetero-junction TFETs is much more difficult due to
process immaturity in comparison to Si-TFETs, which can be implemented using a
process similar to Si-CMOS. This work focuses on the design of Si-TFET integrated
circuits for applications where these circuits outperform CMOS and the combination
of the two achieves both performance and power savings on the same chip.