10
2 State-of-the-Art TFET Devices
Fig. 2.7 32 nm TFET and
PTM MOSFET I D (V GS );
V DS step: 0.25 V [©2016
IEEE]
V GS (V)
I D (A/μm)
-1.0
V DS = -0.25V
step -0.25V
10
-03
10
-05
10
-07
10
-09
10
-11
10
-13
10
-15
10
-17
pMOS
PTM
pTFET
Sims.
V OFF
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
pTFET
Meas.
Fig. 2.8 Output
characteristics of the TFET
for forward biasing; I D (V DS )
[©2016 IEEE]
-0.25 V
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
pTFET
Sims.
Super-linear
regime
Poor saturation
regime
V GS = -1.0V
V DS (V)
I D (mA/μm)
by the fact that the forward output characteristics I D (V DS ) of the TFET does not
saturate as shown in Fig. 2.8. On the simulated reverse output characteristics of the
PTFET plotted in Fig. 2.9 it can be observed that similar to the NTFET the current
is important for two biasing conditions: (1) at low positive (negative for an NTFET)
V DS , when the current is dominated by BTBT, and (2) at high positive (negative for
an NTFET) V DS , when the turn-on of the p-i-n junction occurs as it is now biased
in forward mode. In the latter bias condition the gate has little control on the device
current, see Fig. 2.9. In literature, this behavior is called unidirectional as the gate
controls the characteristics of TFET only in the forward regime, Figs. 2.7 and 2.8,
and not in the reverse regime, Fig. 2.9. Therefore, TFETs should not be biased in
reverse with high negative V DS for NTFETs (positive V DS for PTFET) to avoid
high-leakage currents, as can be seen in Fig. 2.9.
The total gate capacitance of a PTFET in comparison with that of a pMOSFET
is plotted in Fig. 2.10. It can be noticed that the capacitance of a PTFET diminishes,
for a given V GS value, as the drain voltage |V DS | is increased when conducting in