1 Introduction
3
is the ON current, which is lower than CMOS. However, a few recent reports
demonstrated fabricated TFETs with drain currents up to 760 µA/µm [15] and
subthreshold slopes as low as 30 mV/decade [16].
These results confirm the TFET’s potential for successful utilization in lowpower/standby power applications and encouraged research on TFET circuits.
Our goal is aligned with the reports present in literature and our efforts aim to
explore technology and circuit architectures including memories, with reduced
power consumption, especially static power, low area, and high speed of operation.
From the above considerations TFETs fit very well the chip power/cost profile
that is imposed by IoT and WSN applications. However, TFETs are significantly
slower than CMOS [17], in spite of device improvements demonstrated recently
[1, 14, 15]. Although the recent work on TFETs has targeted the same devicelevel goals as CMOS transistors along the International Technology Roadmap for
Semiconductors (ITRS) [3], our vision is that TFETs will not replace CMOS, rather
they will complement it. Instead of simplistically trying to match and replace CMOS,
our vision permits to retain the benefits of a mature technology such as CMOS and
the related existing ecosystem, while leveraging the unique properties and the true
potential of TFETs, which have a far lower leakage but lower speed.
The focus of this text is the exploration of new solutions for low-power circuits
using TFETs while at the same time addressing critical issues at circuit and
architecture level. In our research work we analyzed and proposed topologies
and architectures for various kind of circuits, including SRAMs, CAMs, TCAMs,
DRAMs, flip-flops, latches, and sense amplifiers for sub-32 nm technologies.
The book is organized as follows. Chapter 2 introduces the TFET device
and its characteristics; the TCAD device used in developing the circuits in the
following chapters is described along with its compact model for simulation and
its performance evaluation. Chapter 3 targets the investigation of Silicon-TFET
circuits, compatible with CMOS, for Low STandby Power (LSTP) applications with
ultra-low leakage for long battery life and/or energy harvesting. We analyze the
architecture-level issues in known TFET SRAM designs, propose new TFET cells
followed by developing hybrid architectures with CMOS to optimize speed, power,
and area.
In Chap. 4 architectures/circuits are explored using a unique property of TFETs,
Negative Differential Resistance (NDR), and capacitor leakage. Novel TFET
DRAM, SRAM, and CAM cells are proposed.
In Chap. 5 the exploration of TFET architectures/circuits using NDR is extended
to flip-flops. A novel flip-flop design with low voltage, low power, and high-speed
operation is proposed and compared with the state of the art.
In Chap. 6 the circuit architectures are extended to full integration in a CMOS
platform to make them useful for existing technologies and products. Different
CMOS architectures extended from TFET research and new architectures applicable
to both TFET and CMOS are proposed. Circuits such as reconfigurable-CAMs,
adaptive read for memories and approximate-search CAMs are proposed and
designed to be implemented in a 28 nm FDSOI-CMOS process. The circuit and
layout design is performed using sub-32 nm TFETs [14] and 28 nm FDSOI CMOS
3
is the ON current, which is lower than CMOS. However, a few recent reports
demonstrated fabricated TFETs with drain currents up to 760 µA/µm [15] and
subthreshold slopes as low as 30 mV/decade [16].
These results confirm the TFET’s potential for successful utilization in lowpower/standby power applications and encouraged research on TFET circuits.
Our goal is aligned with the reports present in literature and our efforts aim to
explore technology and circuit architectures including memories, with reduced
power consumption, especially static power, low area, and high speed of operation.
From the above considerations TFETs fit very well the chip power/cost profile
that is imposed by IoT and WSN applications. However, TFETs are significantly
slower than CMOS [17], in spite of device improvements demonstrated recently
[1, 14, 15]. Although the recent work on TFETs has targeted the same devicelevel goals as CMOS transistors along the International Technology Roadmap for
Semiconductors (ITRS) [3], our vision is that TFETs will not replace CMOS, rather
they will complement it. Instead of simplistically trying to match and replace CMOS,
our vision permits to retain the benefits of a mature technology such as CMOS and
the related existing ecosystem, while leveraging the unique properties and the true
potential of TFETs, which have a far lower leakage but lower speed.
The focus of this text is the exploration of new solutions for low-power circuits
using TFETs while at the same time addressing critical issues at circuit and
architecture level. In our research work we analyzed and proposed topologies
and architectures for various kind of circuits, including SRAMs, CAMs, TCAMs,
DRAMs, flip-flops, latches, and sense amplifiers for sub-32 nm technologies.
The book is organized as follows. Chapter 2 introduces the TFET device
and its characteristics; the TCAD device used in developing the circuits in the
following chapters is described along with its compact model for simulation and
its performance evaluation. Chapter 3 targets the investigation of Silicon-TFET
circuits, compatible with CMOS, for Low STandby Power (LSTP) applications with
ultra-low leakage for long battery life and/or energy harvesting. We analyze the
architecture-level issues in known TFET SRAM designs, propose new TFET cells
followed by developing hybrid architectures with CMOS to optimize speed, power,
and area.
In Chap. 4 architectures/circuits are explored using a unique property of TFETs,
Negative Differential Resistance (NDR), and capacitor leakage. Novel TFET
DRAM, SRAM, and CAM cells are proposed.
In Chap. 5 the exploration of TFET architectures/circuits using NDR is extended
to flip-flops. A novel flip-flop design with low voltage, low power, and high-speed
operation is proposed and compared with the state of the art.
In Chap. 6 the circuit architectures are extended to full integration in a CMOS
platform to make them useful for existing technologies and products. Different
CMOS architectures extended from TFET research and new architectures applicable
to both TFET and CMOS are proposed. Circuits such as reconfigurable-CAMs,
adaptive read for memories and approximate-search CAMs are proposed and
designed to be implemented in a 28 nm FDSOI-CMOS process. The circuit and
layout design is performed using sub-32 nm TFETs [14] and 28 nm FDSOI CMOS