2
1 Introduction
scaling are now planned to be in the order of 3X in the next decade [3]. In
other words, the traditional reliance on CMOS technology scaling is definitely an
inadequate approach from the perspective of the IoT evolution, and much greater
reductions in consumption need to come from combined technology, circuit and
architectural breakthroughs [2]. Also, since IoT and WSNs need to be generally
inexpensive (in the dollar range), compatibility with CMOS technology is a must.
Due to the above-mentioned factors efforts were made at both system and
circuit level to optimize both dynamic and static power consumption using various techniques such as dynamic-voltage-frequency-scaling (DVFS), power gating,
reconfigurable computing with shared resources [4–6], high-throughput and small
area embedded-DRAMs [7], and sacrificing area to reduce leakage while maintaining sufficient performance [8]. DVFS is a particularly important technique in
the IoT world due to the operating-mode-dependent frequency requirement, which
ranges from kHz to MHz. Digital systems consist mainly of logic gates, flip-flops,
and memories; therefore, power optimization of each of these components is an
important design aspect. One approach proposed for logic [9] is to use power-gated
standard cells for reducing standby leakage.
For IoT applications, optimizing memory power is of critical concern as more
than 50% and 90% of total power consumption and leakage in standby, respectively,
is in memory [10, 11]. In [11] the authors reported processors with 39% and 51% of
total standby power dissipated in instruction memory and data memory, respectively.
Moreover, in processors significant die area is consumed by cache memories; as an
example a 37.5 MB cache consumes more than 25% of the die area [7]. Thus, it is
of the utmost importance to optimize memory area and leakage power consumption
simultaneously.
In memories, leakage reduction at the cost of bitcell area increase is an inefficient
optimization method because a larger size bitcell results in significant area penalty
at array level. Therefore, lowering the voltage of operation is a widely used leakage
reduction technique in memories. However, this causes bitcell stability issues at
low voltage forcing the designers to use either assist techniques or bigger bitcells.
Moreover, the bigger footprint and power budget of SRAMs are forcing designers to
limit the total on-chip memory size. These different constraints make SoC memory
design at advanced technology nodes very challenging.
The objective of this book is to analyze the potential of devices with very-low
leakage such as Tunnel-Field-Effect Transistors (TFETs) for low-power circuits and
systems applications; these devices have already been proposed as replacement of
standard CMOS for overcoming its limitations. The main focus of the researchers
is to design SRAMs, with compact cells, low power, high speed, and good stability.
The optimizations are done at technology, cell, and architecture levels. But lowpower compact cells with high speed are still missing, especially those with ultralow leakage.
The TFET operates by quantum-tunneling effect, which is different from the
MOSFET working principle. Therefore, TFETs do not suffer from the subthreshold
slope limitation of 60 mV/decade as MOSFETs [12, 13]. While optimized TFETs
can provide leakage currents on the order of fA/µm [14], one major concern
1 Introduction
scaling are now planned to be in the order of 3X in the next decade [3]. In
other words, the traditional reliance on CMOS technology scaling is definitely an
inadequate approach from the perspective of the IoT evolution, and much greater
reductions in consumption need to come from combined technology, circuit and
architectural breakthroughs [2]. Also, since IoT and WSNs need to be generally
inexpensive (in the dollar range), compatibility with CMOS technology is a must.
Due to the above-mentioned factors efforts were made at both system and
circuit level to optimize both dynamic and static power consumption using various techniques such as dynamic-voltage-frequency-scaling (DVFS), power gating,
reconfigurable computing with shared resources [4–6], high-throughput and small
area embedded-DRAMs [7], and sacrificing area to reduce leakage while maintaining sufficient performance [8]. DVFS is a particularly important technique in
the IoT world due to the operating-mode-dependent frequency requirement, which
ranges from kHz to MHz. Digital systems consist mainly of logic gates, flip-flops,
and memories; therefore, power optimization of each of these components is an
important design aspect. One approach proposed for logic [9] is to use power-gated
standard cells for reducing standby leakage.
For IoT applications, optimizing memory power is of critical concern as more
than 50% and 90% of total power consumption and leakage in standby, respectively,
is in memory [10, 11]. In [11] the authors reported processors with 39% and 51% of
total standby power dissipated in instruction memory and data memory, respectively.
Moreover, in processors significant die area is consumed by cache memories; as an
example a 37.5 MB cache consumes more than 25% of the die area [7]. Thus, it is
of the utmost importance to optimize memory area and leakage power consumption
simultaneously.
In memories, leakage reduction at the cost of bitcell area increase is an inefficient
optimization method because a larger size bitcell results in significant area penalty
at array level. Therefore, lowering the voltage of operation is a widely used leakage
reduction technique in memories. However, this causes bitcell stability issues at
low voltage forcing the designers to use either assist techniques or bigger bitcells.
Moreover, the bigger footprint and power budget of SRAMs are forcing designers to
limit the total on-chip memory size. These different constraints make SoC memory
design at advanced technology nodes very challenging.
The objective of this book is to analyze the potential of devices with very-low
leakage such as Tunnel-Field-Effect Transistors (TFETs) for low-power circuits and
systems applications; these devices have already been proposed as replacement of
standard CMOS for overcoming its limitations. The main focus of the researchers
is to design SRAMs, with compact cells, low power, high speed, and good stability.
The optimizations are done at technology, cell, and architecture levels. But lowpower compact cells with high speed are still missing, especially those with ultralow leakage.
The TFET operates by quantum-tunneling effect, which is different from the
MOSFET working principle. Therefore, TFETs do not suffer from the subthreshold
slope limitation of 60 mV/decade as MOSFETs [12, 13]. While optimized TFETs
can provide leakage currents on the order of fA/µm [14], one major concern