Chapter 1
Introduction
Previous trends in System-on-Chip (SoC) design were focused on improving
the performance of the system without giving significant consideration to power
consumption. Complementary-Metal-Oxide-Semiconductor (CMOS) is the widely
accepted technology for designing SoCs for over three decades. Performance
improvements of CMOS systems came mostly through technology scaling and when
speed could not be increased any further, the growing number of transistors per chip,
which followed Moore’s law, led to multi-core processor chips. Technology scaling
significantly improved the system performance and allowed to increase complexity
of systems in cost-effective ways. However, power consumption became the major
constraint in design specifications because of increased leakage with every new
technology node.
The development of energy-efficient systems is becoming ever more important
with widely increasing use of battery-operated systems for applications such as
Internet-of-Things (IoT) and Wireless-Sensor-Nodes (WSN). These systems have
an ever increasing need of energy efficiency for longer battery life time while
maintaining performance to meet the application requirements. Unlike previous
trends in computation focused on increasing the performance at the cost of energy
and area, for applications such as WSN and IoT, system cost, energy efficiency,
and performance are equally important today. To be successful in the market these
new systems should be designed with low power and low cost in mind. IoT and
WSN applications can have periods of low activity and long standby times with
leakage becoming a critical concern for battery life time in SoCs designed for
these applications. Moreover, energy efficiency is becoming increasingly important
because of the ever increasing power density and costly heat sinks required in
compute-intensive systems.
As ultra-low power consumption is a crucial feature of IoT and WSN, they
require major advances in the field of semiconductor devices, integrated circuits,
and system architectures [2], which go well beyond the improvements predicted by
Moore’s law. Indeed, energy/power consumption reductions coming from CMOS
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_1
1
Introduction
Previous trends in System-on-Chip (SoC) design were focused on improving
the performance of the system without giving significant consideration to power
consumption. Complementary-Metal-Oxide-Semiconductor (CMOS) is the widely
accepted technology for designing SoCs for over three decades. Performance
improvements of CMOS systems came mostly through technology scaling and when
speed could not be increased any further, the growing number of transistors per chip,
which followed Moore’s law, led to multi-core processor chips. Technology scaling
significantly improved the system performance and allowed to increase complexity
of systems in cost-effective ways. However, power consumption became the major
constraint in design specifications because of increased leakage with every new
technology node.
The development of energy-efficient systems is becoming ever more important
with widely increasing use of battery-operated systems for applications such as
Internet-of-Things (IoT) and Wireless-Sensor-Nodes (WSN). These systems have
an ever increasing need of energy efficiency for longer battery life time while
maintaining performance to meet the application requirements. Unlike previous
trends in computation focused on increasing the performance at the cost of energy
and area, for applications such as WSN and IoT, system cost, energy efficiency,
and performance are equally important today. To be successful in the market these
new systems should be designed with low power and low cost in mind. IoT and
WSN applications can have periods of low activity and long standby times with
leakage becoming a critical concern for battery life time in SoCs designed for
these applications. Moreover, energy efficiency is becoming increasingly important
because of the ever increasing power density and costly heat sinks required in
compute-intensive systems.
As ultra-low power consumption is a crucial feature of IoT and WSN, they
require major advances in the field of semiconductor devices, integrated circuits,
and system architectures [2], which go well beyond the improvements predicted by
Moore’s law. Indeed, energy/power consumption reductions coming from CMOS
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_1
1