138
Index
Reconfigurable CAM/SRAM
(ReCSAM) (cont.)
write operation, 76–77
TFET/CMOS hybrid, 74
ultra-low leakage, 82
Refresh-free DRAM, 46, 52, 55
Ring oscillator (RO), 11–14
S
Self-tuning memories, 116, 118
Sense amplifier (SA)
adaptive read (see Adaptive read technique)
balanced single-ended, 106
DPSRAM memory, 108, 109
imbalanced, 106, 107
imbalanced SA with open-bitline,
108–110
inverter-based, 105
read scheme, 106
Setup time (T Setup ), 64, 66–70
7T-TFET ternary CAM bitcell, see Ultra-lowpower ternary CAM
Silicon-TFET
CMOS memory circuits, 123
device structure, 8
low-k spacer and high-k gate dielectrics, 8,
9
NTFET, 10
PTFET, 9
reverse biasing, 11
Si-CMOS, 13
SoC, 124
and SPICE model, 11
TCAD simulations, 8
3T-TFET bitcell, 34
turn-on voltage, 8
ULP applications, 59, 60
unidirectional, 10
variations and modelling, 9
Single-ended sensing, 37, 40
charge injection based imbalanced SA,
106–108
conventional differential sensing, 105
differential SA, 105
DPSRAM, 30
imbalanced SA, 84, 85
imbalanced SA with open-bitline, 108–110
inverter-base sensing, 30
optimized TFET memory cells, 105
SA and adaptive memory, 119–120
TFET NDR skewed inverter-based method,
110–113
6T-CMOS CAM bitcell, 74, 91
Skewed inverter based sense amplifier,
110–113
SPICE TFET model, 11
Static noise margin (SNM), 19–21, 26, 33, 36
Static power, 2, 3, 14, 65, 71
Static Random Access Memory (SRAM)
adaptive techniques, 105
conventional ECC, 25
hetero-junction TFET, 21
modified 6T TFET bitcell, 21, 23
multi-port SRAMs, 26
NDR property, 23
on-chip, 45
standard 6T-SRAM-bitcell based design,
124
2TIC uSRAM, 52–54
3T-TFET bitcells (see TFET-CMOS hybrid
SRAM)
4T-NDR TFET bitcells, 24
5T-TFET-CMOS hybrid bitcell, 23
6T-TFET operation
array-based analysis, 19–21
read and write mechanisms, 18
stability, 19
7T-TFET bitcells, 21, 22
8T CMOS SRAM, 25
8T-TFET bitcells, 21, 22
8T-TFET dual-wordline bitcell, 26
uDRAM, 46
System-on-chip (SoC), 1, 45, 59, 73, 74, 124
T
TCAD device, 3, 8, 9, 11
Technology scaling, 1
TFET-CMOS co-integration, 124, 125
TFET-CMOS hybrid memories, 17, 106, 120
TFET-CMOS hybrid SRAM, 17
dynamic power consumption, 34
energy efficiency, 40–42
memory architecture, 38–39
memory layout, 39–40
NDR property, 34
proposed cell architectures, 34, 35
read and write performance (WLPcrit),
42–43
read operation, 35, 37, 38
retention mode and stability, 35–36
write operation, 36–37
TFET NDR based sense amplifier (SA)
DC characteristics, 111
MOSFETs, 112
read scalability, circuit, 111, 112
sense amplifier schematic, 111
Index
Reconfigurable CAM/SRAM
(ReCSAM) (cont.)
write operation, 76–77
TFET/CMOS hybrid, 74
ultra-low leakage, 82
Refresh-free DRAM, 46, 52, 55
Ring oscillator (RO), 11–14
S
Self-tuning memories, 116, 118
Sense amplifier (SA)
adaptive read (see Adaptive read technique)
balanced single-ended, 106
DPSRAM memory, 108, 109
imbalanced, 106, 107
imbalanced SA with open-bitline,
108–110
inverter-based, 105
read scheme, 106
Setup time (T Setup ), 64, 66–70
7T-TFET ternary CAM bitcell, see Ultra-lowpower ternary CAM
Silicon-TFET
CMOS memory circuits, 123
device structure, 8
low-k spacer and high-k gate dielectrics, 8,
9
NTFET, 10
PTFET, 9
reverse biasing, 11
Si-CMOS, 13
SoC, 124
and SPICE model, 11
TCAD simulations, 8
3T-TFET bitcell, 34
turn-on voltage, 8
ULP applications, 59, 60
unidirectional, 10
variations and modelling, 9
Single-ended sensing, 37, 40
charge injection based imbalanced SA,
106–108
conventional differential sensing, 105
differential SA, 105
DPSRAM, 30
imbalanced SA, 84, 85
imbalanced SA with open-bitline, 108–110
inverter-base sensing, 30
optimized TFET memory cells, 105
SA and adaptive memory, 119–120
TFET NDR skewed inverter-based method,
110–113
6T-CMOS CAM bitcell, 74, 91
Skewed inverter based sense amplifier,
110–113
SPICE TFET model, 11
Static noise margin (SNM), 19–21, 26, 33, 36
Static power, 2, 3, 14, 65, 71
Static Random Access Memory (SRAM)
adaptive techniques, 105
conventional ECC, 25
hetero-junction TFET, 21
modified 6T TFET bitcell, 21, 23
multi-port SRAMs, 26
NDR property, 23
on-chip, 45
standard 6T-SRAM-bitcell based design,
124
2TIC uSRAM, 52–54
3T-TFET bitcells (see TFET-CMOS hybrid
SRAM)
4T-NDR TFET bitcells, 24
5T-TFET-CMOS hybrid bitcell, 23
6T-TFET operation
array-based analysis, 19–21
read and write mechanisms, 18
stability, 19
7T-TFET bitcells, 21, 22
8T CMOS SRAM, 25
8T-TFET bitcells, 21, 22
8T-TFET dual-wordline bitcell, 26
uDRAM, 46
System-on-chip (SoC), 1, 45, 59, 73, 74, 124
T
TCAD device, 3, 8, 9, 11
Technology scaling, 1
TFET-CMOS co-integration, 124, 125
TFET-CMOS hybrid memories, 17, 106, 120
TFET-CMOS hybrid SRAM, 17
dynamic power consumption, 34
energy efficiency, 40–42
memory architecture, 38–39
memory layout, 39–40
NDR property, 34
proposed cell architectures, 34, 35
read and write performance (WLPcrit),
42–43
read operation, 35, 37, 38
retention mode and stability, 35–36
write operation, 36–37
TFET NDR based sense amplifier (SA)
DC characteristics, 111
MOSFETs, 112
read scalability, circuit, 111, 112
sense amplifier schematic, 111