Index
137
semi-dynamic design, 61
sense amplifier-based, 61, 62
speed comparison, 62
synchronous logic and microprocessorbased systems, 59
transmission-gate, 60, 61, 68
Fully depleted silicon on insulator (FDSOI),
3–5, 29, 39, 46, 53, 60, 74, 83, 86,
100, 120
G
Gate capacitance, 10, 11
H
Half-selection (HS), 17, 19–20, 25, 30, 32, 76,
77, 93, 95
Heterojunction TFET (HTFET), 5, 13, 21, 61,
70, 123, 127
Hold time, 67
Homojunction TFET, 5, 61
I
Imbalanced sense amplifier
charge-injection based single-ended SA,
30, 106–108
with open-bitline, 108–110
MOS capacitors, 85
read speed with/without SA imbalance
tuning, 87
International Technology Roadmap for
Semiconductors (ITRS), 3
Internet-of-Things (IoT)
cost and power efficiency, 59
DVFS, 2
energy-efficient systems, 1
memory power, optimization, 2
ultra-low power consumption, 1
and WSN, 1
L
Leakage power, 26, 33, 42, 65–67, 70, 74, 75
Low power
CAM-based, 90
dynamic power efficiency, 14
flip-flop designs, 59
LSTP, 3, 15, 17
PDP analysis, 12
SRAM-based, 95
TFETs, 2, 3
3T-TFET SRAM cell, 34
ultra-low power TFET TCAM, 100–103
Low-standby power (LSTP), 3, 15, 17, 125
FinFET-LSTP designs, 65–68
reconfigurability, 74
M
Master-slave flip-flop (MSFF)
TFET-FF design, 63
12-TFETs
energy efficiency, 65–66
flip-flop operation, 64–65
flip-flop performance, 66–68
proposed TFET-FF design, 63, 64
Multi-port SRAMs, 26
N
Negative Differential Resistance (NDR), 3, 7,
23, 46, 55, 60, 100, 125
See also TFET NDR based sense
amplifier (SA)
Negative wordline (NWL), 42, 45, 46
Non-volatile devices, 124
Non-volatile-memory (NVM), 90, 105
N-type (NTFET), 5, 6, 10–12, 22
O
On-chip storage demand, 45
P
Pattern search, 74, 100
Power delay product (PDP), 12
Predictive Technology Model (PTM), 8,
10–12, 14
Pseudo Ternary CAM (TCAM), 74, 82, 86, 89,
100–103
P-type (PTFET), 5, 6, 9–12, 15
R
Read assist (RA), 79, 80, 84, 92, 93, 116
Reconfigurable CAM/SRAM (ReCSAM)
CMOS bitcell, 74, 82 (see also CMOS
reconfigurable CAM/SRAM)
memory array, CAM and SRAM, 74
9T-TFET CAM cell
dual wordline, 75
performance, 79–80
power consumption, 80–82
proposed design, 75, 76
read operation, 75, 77–79
137
semi-dynamic design, 61
sense amplifier-based, 61, 62
speed comparison, 62
synchronous logic and microprocessorbased systems, 59
transmission-gate, 60, 61, 68
Fully depleted silicon on insulator (FDSOI),
3–5, 29, 39, 46, 53, 60, 74, 83, 86,
100, 120
G
Gate capacitance, 10, 11
H
Half-selection (HS), 17, 19–20, 25, 30, 32, 76,
77, 93, 95
Heterojunction TFET (HTFET), 5, 13, 21, 61,
70, 123, 127
Hold time, 67
Homojunction TFET, 5, 61
I
Imbalanced sense amplifier
charge-injection based single-ended SA,
30, 106–108
with open-bitline, 108–110
MOS capacitors, 85
read speed with/without SA imbalance
tuning, 87
International Technology Roadmap for
Semiconductors (ITRS), 3
Internet-of-Things (IoT)
cost and power efficiency, 59
DVFS, 2
energy-efficient systems, 1
memory power, optimization, 2
ultra-low power consumption, 1
and WSN, 1
L
Leakage power, 26, 33, 42, 65–67, 70, 74, 75
Low power
CAM-based, 90
dynamic power efficiency, 14
flip-flop designs, 59
LSTP, 3, 15, 17
PDP analysis, 12
SRAM-based, 95
TFETs, 2, 3
3T-TFET SRAM cell, 34
ultra-low power TFET TCAM, 100–103
Low-standby power (LSTP), 3, 15, 17, 125
FinFET-LSTP designs, 65–68
reconfigurability, 74
M
Master-slave flip-flop (MSFF)
TFET-FF design, 63
12-TFETs
energy efficiency, 65–66
flip-flop operation, 64–65
flip-flop performance, 66–68
proposed TFET-FF design, 63, 64
Multi-port SRAMs, 26
N
Negative Differential Resistance (NDR), 3, 7,
23, 46, 55, 60, 100, 125
See also TFET NDR based sense
amplifier (SA)
Negative wordline (NWL), 42, 45, 46
Non-volatile devices, 124
Non-volatile-memory (NVM), 90, 105
N-type (NTFET), 5, 6, 10–12, 22
O
On-chip storage demand, 45
P
Pattern search, 74, 100
Power delay product (PDP), 12
Predictive Technology Model (PTM), 8,
10–12, 14
Pseudo Ternary CAM (TCAM), 74, 82, 86, 89,
100–103
P-type (PTFET), 5, 6, 9–12, 15
R
Read assist (RA), 79, 80, 84, 92, 93, 116
Reconfigurable CAM/SRAM (ReCSAM)
CMOS bitcell, 74, 82 (see also CMOS
reconfigurable CAM/SRAM)
memory array, CAM and SRAM, 74
9T-TFET CAM cell
dual wordline, 75
performance, 79–80
power consumption, 80–82
proposed design, 75, 76
read operation, 75, 77–79