136
Index
CMOS reconfigurable CAM/SRAM (cont.)
speed improvements, 88
SRAM mode, 86
search speed, 88, 90
Complementary-metal-oxide-semiconductor
(CMOS)
conventional differential sensing, 105
FDSOI, 3–4
flip-flops, 59, 60 (see also Flip-flops,
TFET)
hybrid TFET-CMOS multi-core processor,
124
memory circuits, 123
performance improvements, 1
ReCSAM (see Reconfigurable
CAM/SRAM (ReCSAM))
vs. TFET, 3, 6
dynamic and static power vs. supply
voltage, 14
dynamic performance, 11
Miller capacitance effect, 13
operating frequency, 12
PDP, 12, 13
traditional reliance, 2
Content-addressable memories (CAMs), 3
approximate-search, 74, 100
in ASIC, 73, 90
associative memory architecture (see
Associative memories)
as cache memory, 73
to CMOS on 6T-CMOS bitcell (see CMOS
reconfigurable CAM/SRAM)
flexible architectures, 73
FPGA-based, 73
9T-TFET CAM cell (see Reconfigurable
CAM/SRAM (ReCSAM))
ultra-low-power (see Ultra-low-power
ternary CAM)
Conventional differential sensing, 105
Current-mode WTA circuit, 95, 97, 99
D
Dual data rate (DDR), 46, 52, 55, 57
Dual-port associative memory, 95–97
Dual-port SRAM (DPSRAM)
DVFS, 26
8T-TFET bitcell, 17
8T-TFET dual-port SRAM cell, 28
in embedded systems, 26
32 Kb Mux-8 dual-port memory
architecture, 29
micro-architecture design, 29
and multi-port, 26
open bitlines architecture, 108, 109
performance and stability, 8T DPSRAM,
32–33
proposed TFET cell, 27–29
pseudo dual-port scratchpad, 27
read operation, 29–30
single-ended sensing, 30
write assist, 26
write operation, 30–32
Dynamic power, 9, 11, 13–15, 65, 66, 72, 82,
105, 125
Dynamic random access memory (DRAM), 2,
3
capacitor-less TFET, 46
design challenges, 46
embedded (see Embedded DRAMs
(eDRAMs))
and Flash, 124
ultimate (see Ultimate DRAM (uDRAM))
Dynamic voltage frequency scaling (DVFS),
26, 32
EDP-and barrier-aware, 124–125
IoT, 2
E
Effective oxide thickness (EOT), 45, 48, 51, 52
Embedded DRAMs (eDRAMs)
array density, 45
capacitor size, 45–46
and conventional DRAMs, 51
density, 45
EOT, 45
and LVSRAM, 57
NWL, 45
planar process, 46
2T1C uSRAM, 52
Embedded Flash (eFlash), 45
Energy-delay product (EDP), 124
Energy-efficient systems, 1
F
Flip-flops, TFET
CMOS, 59
design-level issues, 60
FinFET, 64–72
limitations, 60
master-slave, 61
with modified latch, 61, 62
MOSFET master-slave pseudo-static D
design, 62
MSFF (see Master-slave flip-flop (MSFF))
pseudo-static flip-flop, 63
Index
CMOS reconfigurable CAM/SRAM (cont.)
speed improvements, 88
SRAM mode, 86
search speed, 88, 90
Complementary-metal-oxide-semiconductor
(CMOS)
conventional differential sensing, 105
FDSOI, 3–4
flip-flops, 59, 60 (see also Flip-flops,
TFET)
hybrid TFET-CMOS multi-core processor,
124
memory circuits, 123
performance improvements, 1
ReCSAM (see Reconfigurable
CAM/SRAM (ReCSAM))
vs. TFET, 3, 6
dynamic and static power vs. supply
voltage, 14
dynamic performance, 11
Miller capacitance effect, 13
operating frequency, 12
PDP, 12, 13
traditional reliance, 2
Content-addressable memories (CAMs), 3
approximate-search, 74, 100
in ASIC, 73, 90
associative memory architecture (see
Associative memories)
as cache memory, 73
to CMOS on 6T-CMOS bitcell (see CMOS
reconfigurable CAM/SRAM)
flexible architectures, 73
FPGA-based, 73
9T-TFET CAM cell (see Reconfigurable
CAM/SRAM (ReCSAM))
ultra-low-power (see Ultra-low-power
ternary CAM)
Conventional differential sensing, 105
Current-mode WTA circuit, 95, 97, 99
D
Dual data rate (DDR), 46, 52, 55, 57
Dual-port associative memory, 95–97
Dual-port SRAM (DPSRAM)
DVFS, 26
8T-TFET bitcell, 17
8T-TFET dual-port SRAM cell, 28
in embedded systems, 26
32 Kb Mux-8 dual-port memory
architecture, 29
micro-architecture design, 29
and multi-port, 26
open bitlines architecture, 108, 109
performance and stability, 8T DPSRAM,
32–33
proposed TFET cell, 27–29
pseudo dual-port scratchpad, 27
read operation, 29–30
single-ended sensing, 30
write assist, 26
write operation, 30–32
Dynamic power, 9, 11, 13–15, 65, 66, 72, 82,
105, 125
Dynamic random access memory (DRAM), 2,
3
capacitor-less TFET, 46
design challenges, 46
embedded (see Embedded DRAMs
(eDRAMs))
and Flash, 124
ultimate (see Ultimate DRAM (uDRAM))
Dynamic voltage frequency scaling (DVFS),
26, 32
EDP-and barrier-aware, 124–125
IoT, 2
E
Effective oxide thickness (EOT), 45, 48, 51, 52
Embedded DRAMs (eDRAMs)
array density, 45
capacitor size, 45–46
and conventional DRAMs, 51
density, 45
EOT, 45
and LVSRAM, 57
NWL, 45
planar process, 46
2T1C uSRAM, 52
Embedded Flash (eFlash), 45
Energy-delay product (EDP), 124
Energy-efficient systems, 1
F
Flip-flops, TFET
CMOS, 59
design-level issues, 60
FinFET, 64–72
limitations, 60
master-slave, 61
with modified latch, 61, 62
MOSFET master-slave pseudo-static D
design, 62
MSFF (see Master-slave flip-flop (MSFF))
pseudo-static flip-flop, 63