Index
A
Adaptive memories, 105, 106, 114, 119, 121
Adaptive read technique, 105
asynchronous memory design, 119–120
AVS, 113
bitline discharge, 113
differential voltage (Vdiff), 113
functionality
operation RdOK, 115
RdOK signal generation, 116
read operations, 114
self-adapting SRAM using RdOK,
117–119
SRAM with self-tuning using RdOK,
116–117
operation, SA, 113–114
proposed SA, 114
Advance voltage scaling (AVS), 113
Ambipolar effect, 6–8
Approximate-search, 3, 74, 100
Array-based 6T TFET SRAM
3 × 3 bitcell array, 20
corner cells RET, 19
HS problem, 19–20
nine-cell fragment, 19
WD problem, 20–21
Associative memories
with CMOS CAM bitcell
associative search operation, 92–94
optimized comparison logic, 90
6T-CAM bitcell, 90, 91
two-bit WTA-based comparison logic,
91, 92
write operation, 94–95
current-mode WTA logic, 97–100
8T-TFET associative memory bitcell, 74,
95–97
neuromorphic implementations, 90
read technique, 119
ReRAMs, 90
search applications, 90
standard 10T-NOR CAM bitcell, 97
STTRAMs, 90
B
Band to band tunneling (BTBT), 5–7, 10
Battery-powered devices, 124
Binary CAM (BCAM), 83–85
Built-in-self-test (BIST), 106, 116
C
Charge-injection sense amplifier
MOS capacitors, 84
MOSFET capacitors, 107
single-ended imbalanced SA, 30, 106–108
with open-bitline, 108–110
CMOS reconfigurable CAM/SRAM
comparison, 88, 89
design, 82
high-speed 6T-CMOS, 88
match line, 82
read/write/search test patterns, 86
ReCSAM architecture
BCAM, 83–85
imbalance tuning (IT), 86–87
memory organization, 83
pseudo-TCAM mode, 86
single-bitline configuration, 83
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3
135
A
Adaptive memories, 105, 106, 114, 119, 121
Adaptive read technique, 105
asynchronous memory design, 119–120
AVS, 113
bitline discharge, 113
differential voltage (Vdiff), 113
functionality
operation RdOK, 115
RdOK signal generation, 116
read operations, 114
self-adapting SRAM using RdOK,
117–119
SRAM with self-tuning using RdOK,
116–117
operation, SA, 113–114
proposed SA, 114
Advance voltage scaling (AVS), 113
Ambipolar effect, 6–8
Approximate-search, 3, 74, 100
Array-based 6T TFET SRAM
3 × 3 bitcell array, 20
corner cells RET, 19
HS problem, 19–20
nine-cell fragment, 19
WD problem, 20–21
Associative memories
with CMOS CAM bitcell
associative search operation, 92–94
optimized comparison logic, 90
6T-CAM bitcell, 90, 91
two-bit WTA-based comparison logic,
91, 92
write operation, 94–95
current-mode WTA logic, 97–100
8T-TFET associative memory bitcell, 74,
95–97
neuromorphic implementations, 90
read technique, 119
ReRAMs, 90
search applications, 90
standard 10T-NOR CAM bitcell, 97
STTRAMs, 90
B
Band to band tunneling (BTBT), 5–7, 10
Battery-powered devices, 124
Binary CAM (BCAM), 83–85
Built-in-self-test (BIST), 106, 116
C
Charge-injection sense amplifier
MOS capacitors, 84
MOSFET capacitors, 107
single-ended imbalanced SA, 30, 106–108
with open-bitline, 108–110
CMOS reconfigurable CAM/SRAM
comparison, 88, 89
design, 82
high-speed 6T-CMOS, 88
match line, 82
read/write/search test patterns, 86
ReCSAM architecture
BCAM, 83–85
imbalance tuning (IT), 86–87
memory organization, 83
pseudo-TCAM mode, 86
single-bitline configuration, 83
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3
135