Index
139
sensing method, 111–112
TFET-CMOS circuit, 112
trip points, 112
ultra-compact skewed inverter-based
sensing method, 110
Transmission gate flip-flop, 60, 61, 68
Tri-state TFET inverter, 61, 63, 64, 71, 110
Tri-state TFET latch, 63, 64, 71
Tunnel-field-effect-transistors (TFET)
ambipolar effect, 6, 7
battery-powered applications, 124
vs. CMOS, 3, 6
device symbols, 15
EDP-and barrier-aware DVFS, 124–125
flip-flops (see Flip-flops, TFET)
homo-and hetero-junction, 5
I D (V GS ,V DS ) characteristics, 6–11
low-power circuits and systems
applications, 2
in LSTP applications, 17
memory bitcells, 105
and MOSFETs, 5, 7, 46
operation, 5
p-i-n gated junctions, 5
potential, 3
quantum-tunneling effect, 2
ReCSAM (see Reconfigurable
CAM/SRAM (ReCSAM))
in reverse bias, 6, 8
TFET-CMOS hybrid cores, 125
tri-state inverters, 61
12T-TFET master-slave flip-flop (MSFF)
comparison
clock-to-output propagation delay
(T CP 2Q ), 69–70
leakage, 70–71
setup time (T Setup ), 66–70
T Critical , 70
transistor count, 68
energy efficiency, 65–66
flip-flop operation, 64–65
flip-flop performance, 66–68
proposed TFET-FF design, 63, 64
U
Ultimate CAM (uCAM), 54–57
Ultimate DRAM (uDRAM)
advantages, 47
NDR, 46
retention, 47
static latch behavior, 46
1T1C uDRAM cell
advantages, 47
bitcell implementation and
performance, 51–52
memory array organization, 51
NDR, 46
read operation, 49–51
retention, 47
static latch behavior, 46
TFET DRAM bitcell, 47
write operation, 48–49
2T1C uSRAM bitcell
bitcell layout, 54
implementation, 52
memory array organization, 53
RBL and WBL, 52–53
3T1C CAM bitcell, 54–55
TFET DRAM bitcell, 47
write operation, 48–49
Ultimate SRAM (uSRAM), 52–54, 56, 57
Ultra-low power, 1, 34, 100–104
Ultra-low power memories, 17
Ultra-low-power ternary CAM
hybrid TFET/CMOS 7T-TCAM bitcell,
100, 101, 103
memory array organization, 102
multi-bit latch, 101–102
read operation, 101, 102
TCAM cell, 100–101
TCAM dual-bitcell layout, 103
write operation, 101, 102
W
Winner-take-all (WTA) logic, 90–99
Wireless-Sensor Nodes (WSN)
cost and power efficiency, 59
energy-efficient systems, 1
and IoT, 1
ultra-low power consumption, 1
WordLine Pulse width, 29–32, 42, 43
Write assist (WA), 26, 30–32, 43, 79, 80,
106
Write-disturb (WD), 17, 20–22, 25, 28, 30, 32,
79
Write wordline (WWL), 101, 102, 106
139
sensing method, 111–112
TFET-CMOS circuit, 112
trip points, 112
ultra-compact skewed inverter-based
sensing method, 110
Transmission gate flip-flop, 60, 61, 68
Tri-state TFET inverter, 61, 63, 64, 71, 110
Tri-state TFET latch, 63, 64, 71
Tunnel-field-effect-transistors (TFET)
ambipolar effect, 6, 7
battery-powered applications, 124
vs. CMOS, 3, 6
device symbols, 15
EDP-and barrier-aware DVFS, 124–125
flip-flops (see Flip-flops, TFET)
homo-and hetero-junction, 5
I D (V GS ,V DS ) characteristics, 6–11
low-power circuits and systems
applications, 2
in LSTP applications, 17
memory bitcells, 105
and MOSFETs, 5, 7, 46
operation, 5
p-i-n gated junctions, 5
potential, 3
quantum-tunneling effect, 2
ReCSAM (see Reconfigurable
CAM/SRAM (ReCSAM))
in reverse bias, 6, 8
TFET-CMOS hybrid cores, 125
tri-state inverters, 61
12T-TFET master-slave flip-flop (MSFF)
comparison
clock-to-output propagation delay
(T CP 2Q ), 69–70
leakage, 70–71
setup time (T Setup ), 66–70
T Critical , 70
transistor count, 68
energy efficiency, 65–66
flip-flop operation, 64–65
flip-flop performance, 66–68
proposed TFET-FF design, 63, 64
U
Ultimate CAM (uCAM), 54–57
Ultimate DRAM (uDRAM)
advantages, 47
NDR, 46
retention, 47
static latch behavior, 46
1T1C uDRAM cell
advantages, 47
bitcell implementation and
performance, 51–52
memory array organization, 51
NDR, 46
read operation, 49–51
retention, 47
static latch behavior, 46
TFET DRAM bitcell, 47
write operation, 48–49
2T1C uSRAM bitcell
bitcell layout, 54
implementation, 52
memory array organization, 53
RBL and WBL, 52–53
3T1C CAM bitcell, 54–55
TFET DRAM bitcell, 47
write operation, 48–49
Ultimate SRAM (uSRAM), 52–54, 56, 57
Ultra-low power, 1, 34, 100–104
Ultra-low power memories, 17
Ultra-low-power ternary CAM
hybrid TFET/CMOS 7T-TCAM bitcell,
100, 101, 103
memory array organization, 102
multi-bit latch, 101–102
read operation, 101, 102
TCAM cell, 100–101
TCAM dual-bitcell layout, 103
write operation, 101, 102
W
Winner-take-all (WTA) logic, 90–99
Wireless-Sensor Nodes (WSN)
cost and power efficiency, 59
energy-efficient systems, 1
and IoT, 1
ultra-low power consumption, 1
WordLine Pulse width, 29–32, 42, 43
Write assist (WA), 26, 30–32, 43, 79, 80,
106
Write-disturb (WD), 17, 20–22, 25, 28, 30, 32,
79
Write wordline (WWL), 101, 102, 106
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