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flip-flop in sub 100nm technology. In Design Automation, 2006. Asia and South Pacific
Conference on, pages 6–pp. IEEE, 2006.
70. Matthew Cotter, Huichu Liu, Suman Datta, and Vijaykrishnan Narayanan. Evaluation of
tunnel FET-based flip-flop designs for low power, high performance applications. In Quality
electronic design (ISQED), 2013 14th international symposium on, pages 430–437. IEEE,
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71. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel.
Ultra-low-power compact TFET flip-flop design for high-performance low-voltage applications. In Quality Electronic Design (ISQED), 2016 17th International Symposium on, pages
107–112. IEEE, 2016.
72. Greg Burda, Yesh Kolla, Jim Dieffenderfer, and Fadi Hamdan. A 45nm CMOS 13-port 64word 41b fully associative content-addressable register file. In Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), 2010 IEEE International, pages 286–287. IEEE, 2010.
73. Xilinx. XA Zynq-7000 All Programmable SoC First Generation Architecture. www.xilinx.
com
74. Jishen Zhao, Cong Xu, and Yuan Xie. Bandwidth-aware reconfigurable cache design with
hybrid memory technologies. In Proceedings of the International Conference on ComputerAided Design, pages 48–55. IEEE Press, 2011.
75. AD Santana Gil, FJ Quiles Latorre, M Hernandez Calvino, E Herruzo Gomez, and JI Benavides
Benitez. Optimizing the physical implementation of a reconfigurable cache. In Reconfigurable
Computing and FPGAs (ReConFig), 2012 International Conference on, pages 1–6. IEEE,
2012.
76. George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis
Katevenis, Dionisios Pnevmatikatos, and Xiaojun Yang. FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. In Systems,
Architectures, Modeling, and Simulation, 2009. SAMOS’09. International Symposium on,
pages 149–156. IEEE, 2009.
77. Yen-Jen Chang, Kun-Lin Tsai, and Hsiang-Jen Tsai. Low leakage TCAM for IP lookup
using two-side self-gating. IEEE Transactions on Circuits and Systems I: Regular Papers,
60(6):1478–1486, 2013.
78. S Matsunaga, N Sakimura, R Nebashi, Y Tsuji, A Morioka, T Sugibayashi, S Miura, H Honjo,
K Kinoshita, H Sato, et al. Fabrication of a 99%-energy-less nonvolatile multi-functional CAM
chip using hierarchical power gating for a massively-parallel full-text-search engine. In VLSI
Circuits (VLSIC), 2013 Symposium on, pages C106–C107. IEEE, 2013.