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dual-port SRAM with 2.04/spl mu/m/sup 2/8T-thin cell using dynamically-controlled column
bias scheme. In Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC.
2004 IEEE International, pages 508–543. IEEE, 2004.
49. Koji Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, Y Oda, K Usui, T Kawamura, N Tsuboi,
T Iwasaki, K Hashimoto, et al. A 45-nm single-port and dual-port SRAM family with
robust read/write stabilizing circuitry under DVFS environment. In VLSI Circuits, 2008 IEEE
Symposium on, pages 212–213. IEEE, 2008.
50. Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, and
Costin Anghel. Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo Dual Port
scratchpad with GHz speed for embedded applications. In Circuits and Systems (ISCAS), 2015
IEEE International Symposium on, pages 597–600. IEEE, 2015.
51. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Singleended subthreshold SRAM with asymmetrical write/read-assist. IEEE Transactions on Circuits
and Systems I: Regular Papers, 57(12):3039–3047, 2010.
52. Richard F Hobson. A new single-ended SRAM cell with write-assist. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 15(2):173–181, 2007.
53. Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Asymmetrical Write-assist for single-ended SRAM operation. In SOC Conference, 2009. SOCC
2009. IEEE International, pages 101–104. IEEE, 2009.
54. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. 3TTFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applications. In
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pages 361–366.
IEEE, 2016.
55. K Hijioka, N Inoue, I Kume, J Kawahara, N Furutake, H Shirai, T Itoh, T Ogura, K Kazama,
Y Yamamoto, et al. A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for
embedded DRAM with advanced CMOS logics. In Electron Devices Meeting (IEDM), 2010
IEEE International, pages 33–3. IEEE, 2010.
56. John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling,
Abraham Mathews, Toshiaki Kirihata, William R Reohr, Kavita Nair, et al. A 45 nm SOI
embedded DRAM macro for the POWER TM processor 32 MByte on-chip L3 cache. IEEE
Journal of Solid-State Circuits, 46(1):64–75, 2011.
57. Sergey Romanovsky, Atul Katoch, Arun Achyuthan, Cormac O’Connell, Sreedhar Natarajan,
Chris Huang, Chuan-Yu Wu, Min-Jer Wang, CJ Wang, Paul Chen, et al. A 500MHz randomaccess embedded 1Mb DRAM macro in bulk CMOS. In Solid-State Circuits Conference, 2008.
ISSCC 2008. Digest of Technical Papers. IEEE International, pages 270–612. IEEE, 2008.
58. Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B Lal, Nick
Lindert, Mesut Meterelliyoz, Randy B Osborne, Joodong Park, Shigeki Tomishima, et al. A 1
Gb 2 GHz 128 Gb/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology. IEEE
Journal of Solid-State Circuits, 50(1):150–157, 2015.
59. Ruth Brain, A Baran, N Bisnik, H-P Chen, S-J Choi, A Chugh, M Fradkin, T Glassman,
F Hamzaoglu, E Hoggan, et al. A 22nm high performance embedded DRAM SoC technology
featuring tri-gate transistors and MIMCAP COB. In VLSI Circuits (VLSIC), 2013 Symposium
on, pages T16–T17. IEEE, 2013.
60. Yih Wang, Umut Arslan, Nabhendra Bisnik, Ruth Brain, Swaroop Ghosh, Fatih Hamzaoglu,
Nick Lindert, Mesut Meterelliyoz, Joodong Park, Shigeki Tomishima, et al. Retention time
optimization for eDRAM in 22nm tri-gate CMOS technology. In Electron Devices Meeting
(IEDM), 2013 IEEE International, pages 9–5. IEEE, 2013.
61. JEDEC. JEDEC DDR4 SDRAM STANDARD (JEDS79-4). http://www.jdec.org/
62. Arnab Biswas and Adrian M Ionescu. 1T capacitor-less DRAM cell based on asymmetric
tunnel FET design. IEEE Journal of the Electron Devices Society, 3(3):217–222, 2015.
63. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel.
Tunnel FET based refresh-free-DRAM. In Proceedings of the Conference on Design,
Automation & Test in Europe, pages 914–917. European Design and Automation Association,
2017.
References
48. Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, S Imaolka, and Hiroshi Makino. A 90nm
dual-port SRAM with 2.04/spl mu/m/sup 2/8T-thin cell using dynamically-controlled column
bias scheme. In Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC.
2004 IEEE International, pages 508–543. IEEE, 2004.
49. Koji Nii, M Yabuuchi, Y Tsukamoto, S Ohbayashi, Y Oda, K Usui, T Kawamura, N Tsuboi,
T Iwasaki, K Hashimoto, et al. A 45-nm single-port and dual-port SRAM family with
robust read/write stabilizing circuitry under DVFS environment. In VLSI Circuits, 2008 IEEE
Symposium on, pages 212–213. IEEE, 2008.
50. Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, and
Costin Anghel. Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo Dual Port
scratchpad with GHz speed for embedded applications. In Circuits and Systems (ISCAS), 2015
IEEE International Symposium on, pages 597–600. IEEE, 2015.
51. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Singleended subthreshold SRAM with asymmetrical write/read-assist. IEEE Transactions on Circuits
and Systems I: Regular Papers, 57(12):3039–3047, 2010.
52. Richard F Hobson. A new single-ended SRAM cell with write-assist. IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, 15(2):173–181, 2007.
53. Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Asymmetrical Write-assist for single-ended SRAM operation. In SOC Conference, 2009. SOCC
2009. IEEE International, pages 101–104. IEEE, 2009.
54. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. 3TTFET bitcell based TFET-CMOS hybrid SRAM design for ultra-low power applications. In
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pages 361–366.
IEEE, 2016.
55. K Hijioka, N Inoue, I Kume, J Kawahara, N Furutake, H Shirai, T Itoh, T Ogura, K Kazama,
Y Yamamoto, et al. A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for
embedded DRAM with advanced CMOS logics. In Electron Devices Meeting (IEDM), 2010
IEEE International, pages 33–3. IEEE, 2010.
56. John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling,
Abraham Mathews, Toshiaki Kirihata, William R Reohr, Kavita Nair, et al. A 45 nm SOI
embedded DRAM macro for the POWER TM processor 32 MByte on-chip L3 cache. IEEE
Journal of Solid-State Circuits, 46(1):64–75, 2011.
57. Sergey Romanovsky, Atul Katoch, Arun Achyuthan, Cormac O’Connell, Sreedhar Natarajan,
Chris Huang, Chuan-Yu Wu, Min-Jer Wang, CJ Wang, Paul Chen, et al. A 500MHz randomaccess embedded 1Mb DRAM macro in bulk CMOS. In Solid-State Circuits Conference, 2008.
ISSCC 2008. Digest of Technical Papers. IEEE International, pages 270–612. IEEE, 2008.
58. Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B Lal, Nick
Lindert, Mesut Meterelliyoz, Randy B Osborne, Joodong Park, Shigeki Tomishima, et al. A 1
Gb 2 GHz 128 Gb/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology. IEEE
Journal of Solid-State Circuits, 50(1):150–157, 2015.
59. Ruth Brain, A Baran, N Bisnik, H-P Chen, S-J Choi, A Chugh, M Fradkin, T Glassman,
F Hamzaoglu, E Hoggan, et al. A 22nm high performance embedded DRAM SoC technology
featuring tri-gate transistors and MIMCAP COB. In VLSI Circuits (VLSIC), 2013 Symposium
on, pages T16–T17. IEEE, 2013.
60. Yih Wang, Umut Arslan, Nabhendra Bisnik, Ruth Brain, Swaroop Ghosh, Fatih Hamzaoglu,
Nick Lindert, Mesut Meterelliyoz, Joodong Park, Shigeki Tomishima, et al. Retention time
optimization for eDRAM in 22nm tri-gate CMOS technology. In Electron Devices Meeting
(IEDM), 2013 IEEE International, pages 9–5. IEEE, 2013.
61. JEDEC. JEDEC DDR4 SDRAM STANDARD (JEDS79-4). http://www.jdec.org/
62. Arnab Biswas and Adrian M Ionescu. 1T capacitor-less DRAM cell based on asymmetric
tunnel FET design. IEEE Journal of the Electron Devices Society, 3(3):217–222, 2015.
63. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel.
Tunnel FET based refresh-free-DRAM. In Proceedings of the Conference on Design,
Automation & Test in Europe, pages 914–917. European Design and Automation Association,
2017.