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42. Jose Maiz, Scott Hareland, Kevin Zhang, and Patrick Armstrong. Characterization of multi-bit
soft error events in advanced SRAMs. In Electron Devices Meeting, 2003. IEDM’03 Technical
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43. Peter Hazucha, T Karnik, J Maiz, S Walstra, B Bloechel, J Tschanz, G Dermer, S Hareland,
P Armstrong, and S Borkar. Neutron soft error rate measurements in a 90-nm CMOS process
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45. Huichu Liu, Matthew Cotter, Suman Datta, and Vijaykrishnan Narayanan. Soft-error performance evaluation on emerging low power devices. IEEE Transactions on Device and Materials
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46. Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji
Nii, Hiroshi Kawaguchi, and Masahiko Yoshimoto. Which is the Best Dual-Port SRAM in 45nm Process Technology? 8T, 10T single end, and 10T differential. In Integrated Circuit Design
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129
31. Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J Koester, Dennis
Sylvester, and David Blaauw. Low power circuit design based on heterojunction tunneling
transistors (HETTs). In Proceedings of the 2009 ACM/IEEE international symposium on Low
power electronics and design, pages 219–224. ACM, 2009.
32. Adam Makosiej, Rutwick Kumar Kashyap, Andrei Vladimirescu, Amara Amara, and Costin
Anghel. A 32nm tunnel FET SRAM for ultra low leakage. In Circuits and Systems (ISCAS),
2012 IEEE International Symposium on, pages 2517–2520. IEEE, 2012.
33. Alan C Seabaugh and Qin Zhang. Low-voltage tunnel transistors for beyond CMOS logic.
Proceedings of the IEEE, 98(12):2095–2110, 2010.
34. Xuebei Yang and Kartik Mohanram. Robust 6T Si tunneling transistor SRAM design. In
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, pages 1–6.
IEEE, 2011.
35. Jan M Rabaey, Anantha P Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits, A
Design Perspective. Prentice hall Englewood Cliffs, Second edition, 2002.
36. Leland Chang, David M Fried, Jack Hergenrother, Jeffrey W Sleight, Robert H Dennard,
Robert K Montoye, Lidija Sekaric, Sharee J McNab, Anna W Topol, Charlotte D Adams,
et al. Stable SRAM cell design for the 32 nm node and beyond. In VLSI Technology, 2005.
Digest of Technical Papers. 2005 Symposium on, pages 128–129. IEEE, 2005.
37. O Thomas, C Anghel, and Adam Makosiej. Cellule memoire a transistors de lecture de type
TFET et MOSFET, 2014. European Patent Application EP3010022A1.
38. V Saripalli et al. Generic TFET based 4T memory devices. US Patent-Issued, No. US8638591,
2014.
39. Leland Chang, Yutaka Nakamura, Robert K Montoye, Jun Sawada, Andrew K Martin,
Kiyofumi Kinoshita, Fadi H Gebara, Kanak B Agarwal, Dhruva J Acharyya, Wilfried Haensch,
et al. A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS. In VLSI Circuits,
2007 IEEE Symposium on, pages 252–253. IEEE, 2007.
40. Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi
Kawaguchi, and Masahiko Yoshimoto. An area-conscious low-voltage-oriented 8T-SRAM
design under DVS environment. In VLSI Circuits, 2007 IEEE Symposium on, pages 256–257.
IEEE, 2007.
41. S Yoshimoto, M Terada, S Okumura, T Suzuki, S Miyano, H Kawaguchi, and M Yoshimoto.
A 40-nm 0.5-V 20.1-μW/MHz 8T SRAM with low-energy disturb mitigation scheme. In VLSI
Circuits (VLSIC), 2011 Symposium on, pages 72–73. IEEE, 2011.
42. Jose Maiz, Scott Hareland, Kevin Zhang, and Patrick Armstrong. Characterization of multi-bit
soft error events in advanced SRAMs. In Electron Devices Meeting, 2003. IEDM’03 Technical
Digest. IEEE International, pages 21–4. IEEE, 2003.
43. Peter Hazucha, T Karnik, J Maiz, S Walstra, B Bloechel, J Tschanz, G Dermer, S Hareland,
P Armstrong, and S Borkar. Neutron soft error rate measurements in a 90-nm CMOS process
and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation. In Electron Devices
Meeting, 2003. IEDM’03 Technical Digest. IEEE International, pages 21–5. IEEE, 2003.
44. Huichu Liu, Matthew Cotter, Suman Datta, and Vijay Narayanan. Technology assessment of Si
and III-V FinFETs and III-V tunnel FETs from soft error rate perspective. In Electron Devices
Meeting (IEDM), 2012 IEEE International, pages 25–5. IEEE, 2012.
45. Huichu Liu, Matthew Cotter, Suman Datta, and Vijaykrishnan Narayanan. Soft-error performance evaluation on emerging low power devices. IEEE Transactions on Device and Materials
Reliability, 14(2):732–741, 2014.
46. Hiroki Noguchi, Shunsuke Okumura, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji
Nii, Hiroshi Kawaguchi, and Masahiko Yoshimoto. Which is the Best Dual-Port SRAM in 45nm Process Technology? 8T, 10T single end, and 10T differential. In Integrated Circuit Design
and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on, pages
55–58. IEEE, 2008.
47. Jui-Jen Wu, Meng-Fan Chang, Shau-Wei Lu, Robert Lo, and Quincy Li. A 45-nm dual-port
SRAM utilizing write-assist cells against simultaneous access disturbances. IEEE Transactions
on Circuits and Systems II: Express Briefs, 59(11):790–794, 2012.